/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * stmp3600 version: 2.4.0
 * stmp3600 authors: Amaury Pouly
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_STMP3600_APBH_H__
#define __HEADERGEN_STMP3600_APBH_H__

#define HW_APBH_CTRL0                           HW(APBH_CTRL0)
#define HWA_APBH_CTRL0                          (0x80004000 + 0x0)
#define HWT_APBH_CTRL0                          HWIO_32_RW
#define HWN_APBH_CTRL0                          APBH_CTRL0
#define HWI_APBH_CTRL0                          
#define HW_APBH_CTRL0_SET                       HW(APBH_CTRL0_SET)
#define HWA_APBH_CTRL0_SET                      (HWA_APBH_CTRL0 + 0x4)
#define HWT_APBH_CTRL0_SET                      HWIO_32_WO
#define HWN_APBH_CTRL0_SET                      APBH_CTRL0
#define HWI_APBH_CTRL0_SET                      
#define HW_APBH_CTRL0_CLR                       HW(APBH_CTRL0_CLR)
#define HWA_APBH_CTRL0_CLR                      (HWA_APBH_CTRL0 + 0x8)
#define HWT_APBH_CTRL0_CLR                      HWIO_32_WO
#define HWN_APBH_CTRL0_CLR                      APBH_CTRL0
#define HWI_APBH_CTRL0_CLR                      
#define HW_APBH_CTRL0_TOG                       HW(APBH_CTRL0_TOG)
#define HWA_APBH_CTRL0_TOG                      (HWA_APBH_CTRL0 + 0xc)
#define HWT_APBH_CTRL0_TOG                      HWIO_32_WO
#define HWN_APBH_CTRL0_TOG                      APBH_CTRL0
#define HWI_APBH_CTRL0_TOG                      
#define BP_APBH_CTRL0_SFTRST                    31
#define BM_APBH_CTRL0_SFTRST                    0x80000000
#define BF_APBH_CTRL0_SFTRST(v)                 (((v) & 0x1) << 31)
#define BFM_APBH_CTRL0_SFTRST(v)                BM_APBH_CTRL0_SFTRST
#define BF_APBH_CTRL0_SFTRST_V(e)               BF_APBH_CTRL0_SFTRST(BV_APBH_CTRL0_SFTRST__##e)
#define BFM_APBH_CTRL0_SFTRST_V(v)              BM_APBH_CTRL0_SFTRST
#define BP_APBH_CTRL0_CLKGATE                   30
#define BM_APBH_CTRL0_CLKGATE                   0x40000000
#define BF_APBH_CTRL0_CLKGATE(v)                (((v) & 0x1) << 30)
#define BFM_APBH_CTRL0_CLKGATE(v)               BM_APBH_CTRL0_CLKGATE
#define BF_APBH_CTRL0_CLKGATE_V(e)              BF_APBH_CTRL0_CLKGATE(BV_APBH_CTRL0_CLKGATE__##e)
#define BFM_APBH_CTRL0_CLKGATE_V(v)             BM_APBH_CTRL0_CLKGATE
#define BP_APBH_CTRL0_RESET_CHANNEL             16
#define BM_APBH_CTRL0_RESET_CHANNEL             0xff0000
#define BV_APBH_CTRL0_RESET_CHANNEL__HWECC      0x1
#define BV_APBH_CTRL0_RESET_CHANNEL__SSP        0x2
#define BV_APBH_CTRL0_RESET_CHANNEL__SRC        0x4
#define BV_APBH_CTRL0_RESET_CHANNEL__DEST       0x8
#define BV_APBH_CTRL0_RESET_CHANNEL__ATA        0x10
#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0      0x10
#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1      0x20
#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2      0x30
#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3      0x40
#define BF_APBH_CTRL0_RESET_CHANNEL(v)          (((v) & 0xff) << 16)
#define BFM_APBH_CTRL0_RESET_CHANNEL(v)         BM_APBH_CTRL0_RESET_CHANNEL
#define BF_APBH_CTRL0_RESET_CHANNEL_V(e)        BF_APBH_CTRL0_RESET_CHANNEL(BV_APBH_CTRL0_RESET_CHANNEL__##e)
#define BFM_APBH_CTRL0_RESET_CHANNEL_V(v)       BM_APBH_CTRL0_RESET_CHANNEL
#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
#define BM_APBH_CTRL0_CLKGATE_CHANNEL           0xff00
#define BV_APBH_CTRL0_CLKGATE_CHANNEL__HWECC    0x1
#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP      0x2
#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SRC      0x4
#define BV_APBH_CTRL0_CLKGATE_CHANNEL__DEST     0x8
#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA      0x10
#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0    0x10
#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1    0x20
#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2    0x30
#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3    0x40
#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)        (((v) & 0xff) << 8)
#define BFM_APBH_CTRL0_CLKGATE_CHANNEL(v)       BM_APBH_CTRL0_CLKGATE_CHANNEL
#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(e)      BF_APBH_CTRL0_CLKGATE_CHANNEL(BV_APBH_CTRL0_CLKGATE_CHANNEL__##e)
#define BFM_APBH_CTRL0_CLKGATE_CHANNEL_V(v)     BM_APBH_CTRL0_CLKGATE_CHANNEL
#define BP_APBH_CTRL0_FREEZE_CHANNEL            0
#define BM_APBH_CTRL0_FREEZE_CHANNEL            0xff
#define BV_APBH_CTRL0_FREEZE_CHANNEL__HWECC     0x1
#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP       0x2
#define BV_APBH_CTRL0_FREEZE_CHANNEL__SRC       0x4
#define BV_APBH_CTRL0_FREEZE_CHANNEL__DEST      0x8
#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA       0x10
#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0     0x10
#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1     0x20
#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2     0x30
#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3     0x40
#define BF_APBH_CTRL0_FREEZE_CHANNEL(v)         (((v) & 0xff) << 0)
#define BFM_APBH_CTRL0_FREEZE_CHANNEL(v)        BM_APBH_CTRL0_FREEZE_CHANNEL
#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(e)       BF_APBH_CTRL0_FREEZE_CHANNEL(BV_APBH_CTRL0_FREEZE_CHANNEL__##e)
#define BFM_APBH_CTRL0_FREEZE_CHANNEL_V(v)      BM_APBH_CTRL0_FREEZE_CHANNEL

#define HW_APBH_CTRL1                           HW(APBH_CTRL1)
#define HWA_APBH_CTRL1                          (0x80004000 + 0x10)
#define HWT_APBH_CTRL1                          HWIO_32_RW
#define HWN_APBH_CTRL1                          APBH_CTRL1
#define HWI_APBH_CTRL1                          
#define HW_APBH_CTRL1_SET                       HW(APBH_CTRL1_SET)
#define HWA_APBH_CTRL1_SET                      (HWA_APBH_CTRL1 + 0x4)
#define HWT_APBH_CTRL1_SET                      HWIO_32_WO
#define HWN_APBH_CTRL1_SET                      APBH_CTRL1
#define HWI_APBH_CTRL1_SET                      
#define HW_APBH_CTRL1_CLR                       HW(APBH_CTRL1_CLR)
#define HWA_APBH_CTRL1_CLR                      (HWA_APBH_CTRL1 + 0x8)
#define HWT_APBH_CTRL1_CLR                      HWIO_32_WO
#define HWN_APBH_CTRL1_CLR                      APBH_CTRL1
#define HWI_APBH_CTRL1_CLR                      
#define HW_APBH_CTRL1_TOG                       HW(APBH_CTRL1_TOG)
#define HWA_APBH_CTRL1_TOG                      (HWA_APBH_CTRL1 + 0xc)
#define HWT_APBH_CTRL1_TOG                      HWIO_32_WO
#define HWN_APBH_CTRL1_TOG                      APBH_CTRL1
#define HWI_APBH_CTRL1_TOG                      
#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN        16
#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN        0xff0000
#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v)     (((v) & 0xff) << 16)
#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v)    BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN
#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_V(e)   BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(BV_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN__##e)
#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_V(v)  BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN
#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ           0
#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ           0xff
#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)        (((v) & 0xff) << 0)
#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)       BM_APBH_CTRL1_CH_CMDCMPLT_IRQ
#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_V(e)      BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(BV_APBH_CTRL1_CH_CMDCMPLT_IRQ__##e)
#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_V(v)     BM_APBH_CTRL1_CH_CMDCMPLT_IRQ

#define HW_APBH_DEVSEL              HW(APBH_DEVSEL)
#define HWA_APBH_DEVSEL             (0x80004000 + 0x20)
#define HWT_APBH_DEVSEL             HWIO_32_RW
#define HWN_APBH_DEVSEL             APBH_DEVSEL
#define HWI_APBH_DEVSEL             
#define BP_APBH_DEVSEL_CH7          28
#define BM_APBH_DEVSEL_CH7          0xf0000000
#define BF_APBH_DEVSEL_CH7(v)       (((v) & 0xf) << 28)
#define BFM_APBH_DEVSEL_CH7(v)      BM_APBH_DEVSEL_CH7
#define BF_APBH_DEVSEL_CH7_V(e)     BF_APBH_DEVSEL_CH7(BV_APBH_DEVSEL_CH7__##e)
#define BFM_APBH_DEVSEL_CH7_V(v)    BM_APBH_DEVSEL_CH7
#define BP_APBH_DEVSEL_CH6          24
#define BM_APBH_DEVSEL_CH6          0xf000000
#define BF_APBH_DEVSEL_CH6(v)       (((v) & 0xf) << 24)
#define BFM_APBH_DEVSEL_CH6(v)      BM_APBH_DEVSEL_CH6
#define BF_APBH_DEVSEL_CH6_V(e)     BF_APBH_DEVSEL_CH6(BV_APBH_DEVSEL_CH6__##e)
#define BFM_APBH_DEVSEL_CH6_V(v)    BM_APBH_DEVSEL_CH6
#define BP_APBH_DEVSEL_CH5          20
#define BM_APBH_DEVSEL_CH5          0xf00000
#define BF_APBH_DEVSEL_CH5(v)       (((v) & 0xf) << 20)
#define BFM_APBH_DEVSEL_CH5(v)      BM_APBH_DEVSEL_CH5
#define BF_APBH_DEVSEL_CH5_V(e)     BF_APBH_DEVSEL_CH5(BV_APBH_DEVSEL_CH5__##e)
#define BFM_APBH_DEVSEL_CH5_V(v)    BM_APBH_DEVSEL_CH5
#define BP_APBH_DEVSEL_CH4          16
#define BM_APBH_DEVSEL_CH4          0xf0000
#define BF_APBH_DEVSEL_CH4(v)       (((v) & 0xf) << 16)
#define BFM_APBH_DEVSEL_CH4(v)      BM_APBH_DEVSEL_CH4
#define BF_APBH_DEVSEL_CH4_V(e)     BF_APBH_DEVSEL_CH4(BV_APBH_DEVSEL_CH4__##e)
#define BFM_APBH_DEVSEL_CH4_V(v)    BM_APBH_DEVSEL_CH4
#define BP_APBH_DEVSEL_CH3          12
#define BM_APBH_DEVSEL_CH3          0xf000
#define BF_APBH_DEVSEL_CH3(v)       (((v) & 0xf) << 12)
#define BFM_APBH_DEVSEL_CH3(v)      BM_APBH_DEVSEL_CH3
#define BF_APBH_DEVSEL_CH3_V(e)     BF_APBH_DEVSEL_CH3(BV_APBH_DEVSEL_CH3__##e)
#define BFM_APBH_DEVSEL_CH3_V(v)    BM_APBH_DEVSEL_CH3
#define BP_APBH_DEVSEL_CH2          8
#define BM_APBH_DEVSEL_CH2          0xf00
#define BF_APBH_DEVSEL_CH2(v)       (((v) & 0xf) << 8)
#define BFM_APBH_DEVSEL_CH2(v)      BM_APBH_DEVSEL_CH2
#define BF_APBH_DEVSEL_CH2_V(e)     BF_APBH_DEVSEL_CH2(BV_APBH_DEVSEL_CH2__##e)
#define BFM_APBH_DEVSEL_CH2_V(v)    BM_APBH_DEVSEL_CH2
#define BP_APBH_DEVSEL_CH1          4
#define BM_APBH_DEVSEL_CH1          0xf0
#define BF_APBH_DEVSEL_CH1(v)       (((v) & 0xf) << 4)
#define BFM_APBH_DEVSEL_CH1(v)      BM_APBH_DEVSEL_CH1
#define BF_APBH_DEVSEL_CH1_V(e)     BF_APBH_DEVSEL_CH1(BV_APBH_DEVSEL_CH1__##e)
#define BFM_APBH_DEVSEL_CH1_V(v)    BM_APBH_DEVSEL_CH1
#define BP_APBH_DEVSEL_CH0          0
#define BM_APBH_DEVSEL_CH0          0xf
#define BF_APBH_DEVSEL_CH0(v)       (((v) & 0xf) << 0)
#define BFM_APBH_DEVSEL_CH0(v)      BM_APBH_DEVSEL_CH0
#define BF_APBH_DEVSEL_CH0_V(e)     BF_APBH_DEVSEL_CH0(BV_APBH_DEVSEL_CH0__##e)
#define BFM_APBH_DEVSEL_CH0_V(v)    BM_APBH_DEVSEL_CH0

#define HW_APBH_CHn_DEBUG2(_n1)             HW(APBH_CHn_DEBUG2(_n1))
#define HWA_APBH_CHn_DEBUG2(_n1)            (0x80004000 + 0x90 + (_n1) * 0x70)
#define HWT_APBH_CHn_DEBUG2(_n1)            HWIO_32_RW
#define HWN_APBH_CHn_DEBUG2(_n1)            APBH_CHn_DEBUG2
#define HWI_APBH_CHn_DEBUG2(_n1)            (_n1)
#define BP_APBH_CHn_DEBUG2_APB_BYTES        16
#define BM_APBH_CHn_DEBUG2_APB_BYTES        0xffff0000
#define BF_APBH_CHn_DEBUG2_APB_BYTES(v)     (((v) & 0xffff) << 16)
#define BFM_APBH_CHn_DEBUG2_APB_BYTES(v)    BM_APBH_CHn_DEBUG2_APB_BYTES
#define BF_APBH_CHn_DEBUG2_APB_BYTES_V(e)   BF_APBH_CHn_DEBUG2_APB_BYTES(BV_APBH_CHn_DEBUG2_APB_BYTES__##e)
#define BFM_APBH_CHn_DEBUG2_APB_BYTES_V(v)  BM_APBH_CHn_DEBUG2_APB_BYTES
#define BP_APBH_CHn_DEBUG2_AHB_BYTES        0
#define BM_APBH_CHn_DEBUG2_AHB_BYTES        0xffff
#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v)     (((v) & 0xffff) << 0)
#define BFM_APBH_CHn_DEBUG2_AHB_BYTES(v)    BM_APBH_CHn_DEBUG2_AHB_BYTES
#define BF_APBH_CHn_DEBUG2_AHB_BYTES_V(e)   BF_APBH_CHn_DEBUG2_AHB_BYTES(BV_APBH_CHn_DEBUG2_AHB_BYTES__##e)
#define BFM_APBH_CHn_DEBUG2_AHB_BYTES_V(v)  BM_APBH_CHn_DEBUG2_AHB_BYTES

#define HW_APBH_CHn_CURCMDAR(_n1)           HW(APBH_CHn_CURCMDAR(_n1))
#define HWA_APBH_CHn_CURCMDAR(_n1)          (0x80004000 + 0x30 + (_n1) * 0x70)
#define HWT_APBH_CHn_CURCMDAR(_n1)          HWIO_32_RW
#define HWN_APBH_CHn_CURCMDAR(_n1)          APBH_CHn_CURCMDAR
#define HWI_APBH_CHn_CURCMDAR(_n1)          (_n1)
#define BP_APBH_CHn_CURCMDAR_CMD_ADDR       0
#define BM_APBH_CHn_CURCMDAR_CMD_ADDR       0xffffffff
#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
#define BFM_APBH_CHn_CURCMDAR_CMD_ADDR(v)   BM_APBH_CHn_CURCMDAR_CMD_ADDR
#define BF_APBH_CHn_CURCMDAR_CMD_ADDR_V(e)  BF_APBH_CHn_CURCMDAR_CMD_ADDR(BV_APBH_CHn_CURCMDAR_CMD_ADDR__##e)
#define BFM_APBH_CHn_CURCMDAR_CMD_ADDR_V(v) BM_APBH_CHn_CURCMDAR_CMD_ADDR

#define HW_APBH_CHn_BAR(_n1)            HW(APBH_CHn_BAR(_n1))
#define HWA_APBH_CHn_BAR(_n1)           (0x80004000 + 0x60 + (_n1) * 0x70)
#define HWT_APBH_CHn_BAR(_n1)           HWIO_32_RW
#define HWN_APBH_CHn_BAR(_n1)           APBH_CHn_BAR
#define HWI_APBH_CHn_BAR(_n1)           (_n1)
#define BP_APBH_CHn_BAR_ADDRESS         0
#define BM_APBH_CHn_BAR_ADDRESS         0xffffffff
#define BF_APBH_CHn_BAR_ADDRESS(v)      (((v) & 0xffffffff) << 0)
#define BFM_APBH_CHn_BAR_ADDRESS(v)     BM_APBH_CHn_BAR_ADDRESS
#define BF_APBH_CHn_BAR_ADDRESS_V(e)    BF_APBH_CHn_BAR_ADDRESS(BV_APBH_CHn_BAR_ADDRESS__##e)
#define BFM_APBH_CHn_BAR_ADDRESS_V(v)   BM_APBH_CHn_BAR_ADDRESS

#define HW_APBH_CHn_CMD(_n1)                    HW(APBH_CHn_CMD(_n1))
#define HWA_APBH_CHn_CMD(_n1)                   (0x80004000 + 0x50 + (_n1) * 0x70)
#define HWT_APBH_CHn_CMD(_n1)                   HWIO_32_RW
#define HWN_APBH_CHn_CMD(_n1)                   APBH_CHn_CMD
#define HWI_APBH_CHn_CMD(_n1)                   (_n1)
#define BP_APBH_CHn_CMD_XFER_COUNT              16
#define BM_APBH_CHn_CMD_XFER_COUNT              0xffff0000
#define BF_APBH_CHn_CMD_XFER_COUNT(v)           (((v) & 0xffff) << 16)
#define BFM_APBH_CHn_CMD_XFER_COUNT(v)          BM_APBH_CHn_CMD_XFER_COUNT
#define BF_APBH_CHn_CMD_XFER_COUNT_V(e)         BF_APBH_CHn_CMD_XFER_COUNT(BV_APBH_CHn_CMD_XFER_COUNT__##e)
#define BFM_APBH_CHn_CMD_XFER_COUNT_V(v)        BM_APBH_CHn_CMD_XFER_COUNT
#define BP_APBH_CHn_CMD_CMDWORDS                12
#define BM_APBH_CHn_CMD_CMDWORDS                0xf000
#define BF_APBH_CHn_CMD_CMDWORDS(v)             (((v) & 0xf) << 12)
#define BFM_APBH_CHn_CMD_CMDWORDS(v)            BM_APBH_CHn_CMD_CMDWORDS
#define BF_APBH_CHn_CMD_CMDWORDS_V(e)           BF_APBH_CHn_CMD_CMDWORDS(BV_APBH_CHn_CMD_CMDWORDS__##e)
#define BFM_APBH_CHn_CMD_CMDWORDS_V(v)          BM_APBH_CHn_CMD_CMDWORDS
#define BP_APBH_CHn_CMD_WAIT4ENDCMD             7
#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x80
#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v)          (((v) & 0x1) << 7)
#define BFM_APBH_CHn_CMD_WAIT4ENDCMD(v)         BM_APBH_CHn_CMD_WAIT4ENDCMD
#define BF_APBH_CHn_CMD_WAIT4ENDCMD_V(e)        BF_APBH_CHn_CMD_WAIT4ENDCMD(BV_APBH_CHn_CMD_WAIT4ENDCMD__##e)
#define BFM_APBH_CHn_CMD_WAIT4ENDCMD_V(v)       BM_APBH_CHn_CMD_WAIT4ENDCMD
#define BP_APBH_CHn_CMD_SEMAPHORE               6
#define BM_APBH_CHn_CMD_SEMAPHORE               0x40
#define BF_APBH_CHn_CMD_SEMAPHORE(v)            (((v) & 0x1) << 6)
#define BFM_APBH_CHn_CMD_SEMAPHORE(v)           BM_APBH_CHn_CMD_SEMAPHORE
#define BF_APBH_CHn_CMD_SEMAPHORE_V(e)          BF_APBH_CHn_CMD_SEMAPHORE(BV_APBH_CHn_CMD_SEMAPHORE__##e)
#define BFM_APBH_CHn_CMD_SEMAPHORE_V(v)         BM_APBH_CHn_CMD_SEMAPHORE
#define BP_APBH_CHn_CMD_NANDWAIT4READY          5
#define BM_APBH_CHn_CMD_NANDWAIT4READY          0x20
#define BF_APBH_CHn_CMD_NANDWAIT4READY(v)       (((v) & 0x1) << 5)
#define BFM_APBH_CHn_CMD_NANDWAIT4READY(v)      BM_APBH_CHn_CMD_NANDWAIT4READY
#define BF_APBH_CHn_CMD_NANDWAIT4READY_V(e)     BF_APBH_CHn_CMD_NANDWAIT4READY(BV_APBH_CHn_CMD_NANDWAIT4READY__##e)
#define BFM_APBH_CHn_CMD_NANDWAIT4READY_V(v)    BM_APBH_CHn_CMD_NANDWAIT4READY
#define BP_APBH_CHn_CMD_NANDLOCK                4
#define BM_APBH_CHn_CMD_NANDLOCK                0x10
#define BF_APBH_CHn_CMD_NANDLOCK(v)             (((v) & 0x1) << 4)
#define BFM_APBH_CHn_CMD_NANDLOCK(v)            BM_APBH_CHn_CMD_NANDLOCK
#define BF_APBH_CHn_CMD_NANDLOCK_V(e)           BF_APBH_CHn_CMD_NANDLOCK(BV_APBH_CHn_CMD_NANDLOCK__##e)
#define BFM_APBH_CHn_CMD_NANDLOCK_V(v)          BM_APBH_CHn_CMD_NANDLOCK
#define BP_APBH_CHn_CMD_IRQONCMPLT              3
#define BM_APBH_CHn_CMD_IRQONCMPLT              0x8
#define BF_APBH_CHn_CMD_IRQONCMPLT(v)           (((v) & 0x1) << 3)
#define BFM_APBH_CHn_CMD_IRQONCMPLT(v)          BM_APBH_CHn_CMD_IRQONCMPLT
#define BF_APBH_CHn_CMD_IRQONCMPLT_V(e)         BF_APBH_CHn_CMD_IRQONCMPLT(BV_APBH_CHn_CMD_IRQONCMPLT__##e)
#define BFM_APBH_CHn_CMD_IRQONCMPLT_V(v)        BM_APBH_CHn_CMD_IRQONCMPLT
#define BP_APBH_CHn_CMD_CHAIN                   2
#define BM_APBH_CHn_CMD_CHAIN                   0x4
#define BF_APBH_CHn_CMD_CHAIN(v)                (((v) & 0x1) << 2)
#define BFM_APBH_CHn_CMD_CHAIN(v)               BM_APBH_CHn_CMD_CHAIN
#define BF_APBH_CHn_CMD_CHAIN_V(e)              BF_APBH_CHn_CMD_CHAIN(BV_APBH_CHn_CMD_CHAIN__##e)
#define BFM_APBH_CHn_CMD_CHAIN_V(v)             BM_APBH_CHn_CMD_CHAIN
#define BP_APBH_CHn_CMD_COMMAND                 0
#define BM_APBH_CHn_CMD_COMMAND                 0x3
#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE      0x1
#define BV_APBH_CHn_CMD_COMMAND__DMA_READ       0x2
#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE      0x3
#define BF_APBH_CHn_CMD_COMMAND(v)              (((v) & 0x3) << 0)
#define BFM_APBH_CHn_CMD_COMMAND(v)             BM_APBH_CHn_CMD_COMMAND
#define BF_APBH_CHn_CMD_COMMAND_V(e)            BF_APBH_CHn_CMD_COMMAND(BV_APBH_CHn_CMD_COMMAND__##e)
#define BFM_APBH_CHn_CMD_COMMAND_V(v)           BM_APBH_CHn_CMD_COMMAND

#define HW_APBH_CHn_NXTCMDAR(_n1)           HW(APBH_CHn_NXTCMDAR(_n1))
#define HWA_APBH_CHn_NXTCMDAR(_n1)          (0x80004000 + 0x40 + (_n1) * 0x70)
#define HWT_APBH_CHn_NXTCMDAR(_n1)          HWIO_32_RW
#define HWN_APBH_CHn_NXTCMDAR(_n1)          APBH_CHn_NXTCMDAR
#define HWI_APBH_CHn_NXTCMDAR(_n1)          (_n1)
#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR       0
#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) & 0xffffffff) << 0)
#define BFM_APBH_CHn_NXTCMDAR_CMD_ADDR(v)   BM_APBH_CHn_NXTCMDAR_CMD_ADDR
#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR_V(e)  BF_APBH_CHn_NXTCMDAR_CMD_ADDR(BV_APBH_CHn_NXTCMDAR_CMD_ADDR__##e)
#define BFM_APBH_CHn_NXTCMDAR_CMD_ADDR_V(v) BM_APBH_CHn_NXTCMDAR_CMD_ADDR

#define HW_APBH_CHn_SEMA(_n1)                   HW(APBH_CHn_SEMA(_n1))
#define HWA_APBH_CHn_SEMA(_n1)                  (0x80004000 + 0x70 + (_n1) * 0x70)
#define HWT_APBH_CHn_SEMA(_n1)                  HWIO_32_RW
#define HWN_APBH_CHn_SEMA(_n1)                  APBH_CHn_SEMA
#define HWI_APBH_CHn_SEMA(_n1)                  (_n1)
#define BP_APBH_CHn_SEMA_PHORE                  16
#define BM_APBH_CHn_SEMA_PHORE                  0xff0000
#define BF_APBH_CHn_SEMA_PHORE(v)               (((v) & 0xff) << 16)
#define BFM_APBH_CHn_SEMA_PHORE(v)              BM_APBH_CHn_SEMA_PHORE
#define BF_APBH_CHn_SEMA_PHORE_V(e)             BF_APBH_CHn_SEMA_PHORE(BV_APBH_CHn_SEMA_PHORE__##e)
#define BFM_APBH_CHn_SEMA_PHORE_V(v)            BM_APBH_CHn_SEMA_PHORE
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA         0
#define BM_APBH_CHn_SEMA_INCREMENT_SEMA         0xff
#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)      (((v) & 0xff) << 0)
#define BFM_APBH_CHn_SEMA_INCREMENT_SEMA(v)     BM_APBH_CHn_SEMA_INCREMENT_SEMA
#define BF_APBH_CHn_SEMA_INCREMENT_SEMA_V(e)    BF_APBH_CHn_SEMA_INCREMENT_SEMA(BV_APBH_CHn_SEMA_INCREMENT_SEMA__##e)
#define BFM_APBH_CHn_SEMA_INCREMENT_SEMA_V(v)   BM_APBH_CHn_SEMA_INCREMENT_SEMA

#define HW_APBH_CHn_DEBUG1(_n1)                         HW(APBH_CHn_DEBUG1(_n1))
#define HWA_APBH_CHn_DEBUG1(_n1)                        (0x80004000 + 0x80 + (_n1) * 0x70)
#define HWT_APBH_CHn_DEBUG1(_n1)                        HWIO_32_RW
#define HWN_APBH_CHn_DEBUG1(_n1)                        APBH_CHn_DEBUG1
#define HWI_APBH_CHn_DEBUG1(_n1)                        (_n1)
#define BP_APBH_CHn_DEBUG1_REQ                          31
#define BM_APBH_CHn_DEBUG1_REQ                          0x80000000
#define BF_APBH_CHn_DEBUG1_REQ(v)                       (((v) & 0x1) << 31)
#define BFM_APBH_CHn_DEBUG1_REQ(v)                      BM_APBH_CHn_DEBUG1_REQ
#define BF_APBH_CHn_DEBUG1_REQ_V(e)                     BF_APBH_CHn_DEBUG1_REQ(BV_APBH_CHn_DEBUG1_REQ__##e)
#define BFM_APBH_CHn_DEBUG1_REQ_V(v)                    BM_APBH_CHn_DEBUG1_REQ
#define BP_APBH_CHn_DEBUG1_BURST                        30
#define BM_APBH_CHn_DEBUG1_BURST                        0x40000000
#define BF_APBH_CHn_DEBUG1_BURST(v)                     (((v) & 0x1) << 30)
#define BFM_APBH_CHn_DEBUG1_BURST(v)                    BM_APBH_CHn_DEBUG1_BURST
#define BF_APBH_CHn_DEBUG1_BURST_V(e)                   BF_APBH_CHn_DEBUG1_BURST(BV_APBH_CHn_DEBUG1_BURST__##e)
#define BFM_APBH_CHn_DEBUG1_BURST_V(v)                  BM_APBH_CHn_DEBUG1_BURST
#define BP_APBH_CHn_DEBUG1_KICK                         29
#define BM_APBH_CHn_DEBUG1_KICK                         0x20000000
#define BF_APBH_CHn_DEBUG1_KICK(v)                      (((v) & 0x1) << 29)
#define BFM_APBH_CHn_DEBUG1_KICK(v)                     BM_APBH_CHn_DEBUG1_KICK
#define BF_APBH_CHn_DEBUG1_KICK_V(e)                    BF_APBH_CHn_DEBUG1_KICK(BV_APBH_CHn_DEBUG1_KICK__##e)
#define BFM_APBH_CHn_DEBUG1_KICK_V(v)                   BM_APBH_CHn_DEBUG1_KICK
#define BP_APBH_CHn_DEBUG1_END                          28
#define BM_APBH_CHn_DEBUG1_END                          0x10000000
#define BF_APBH_CHn_DEBUG1_END(v)                       (((v) & 0x1) << 28)
#define BFM_APBH_CHn_DEBUG1_END(v)                      BM_APBH_CHn_DEBUG1_END
#define BF_APBH_CHn_DEBUG1_END_V(e)                     BF_APBH_CHn_DEBUG1_END(BV_APBH_CHn_DEBUG1_END__##e)
#define BFM_APBH_CHn_DEBUG1_END_V(v)                    BM_APBH_CHn_DEBUG1_END
#define BP_APBH_CHn_DEBUG1_RSVD2                        25
#define BM_APBH_CHn_DEBUG1_RSVD2                        0xe000000
#define BF_APBH_CHn_DEBUG1_RSVD2(v)                     (((v) & 0x7) << 25)
#define BFM_APBH_CHn_DEBUG1_RSVD2(v)                    BM_APBH_CHn_DEBUG1_RSVD2
#define BF_APBH_CHn_DEBUG1_RSVD2_V(e)                   BF_APBH_CHn_DEBUG1_RSVD2(BV_APBH_CHn_DEBUG1_RSVD2__##e)
#define BFM_APBH_CHn_DEBUG1_RSVD2_V(v)                  BM_APBH_CHn_DEBUG1_RSVD2
#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             24
#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) & 0x1) << 24)
#define BFM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)         BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID
#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID_V(e)        BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(BV_APBH_CHn_DEBUG1_NEXTCMDADDRVALID__##e)
#define BFM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID_V(v)       BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID
#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                23
#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) & 0x1) << 23)
#define BFM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)            BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY
#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY_V(e)           BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(BV_APBH_CHn_DEBUG1_RD_FIFO_EMPTY__##e)
#define BFM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY_V(v)          BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY
#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL                 22
#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) & 0x1) << 22)
#define BFM_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)             BM_APBH_CHn_DEBUG1_RD_FIFO_FULL
#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL_V(e)            BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(BV_APBH_CHn_DEBUG1_RD_FIFO_FULL__##e)
#define BFM_APBH_CHn_DEBUG1_RD_FIFO_FULL_V(v)           BM_APBH_CHn_DEBUG1_RD_FIFO_FULL
#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                21
#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) & 0x1) << 21)
#define BFM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)            BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY
#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY_V(e)           BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(BV_APBH_CHn_DEBUG1_WR_FIFO_EMPTY__##e)
#define BFM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY_V(v)          BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY
#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL                 20
#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) & 0x1) << 20)
#define BFM_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)             BM_APBH_CHn_DEBUG1_WR_FIFO_FULL
#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL_V(e)            BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(BV_APBH_CHn_DEBUG1_WR_FIFO_FULL__##e)
#define BFM_APBH_CHn_DEBUG1_WR_FIFO_FULL_V(v)           BM_APBH_CHn_DEBUG1_WR_FIFO_FULL
#define BP_APBH_CHn_DEBUG1_RSVD1                        5
#define BM_APBH_CHn_DEBUG1_RSVD1                        0xfffe0
#define BF_APBH_CHn_DEBUG1_RSVD1(v)                     (((v) & 0x7fff) << 5)
#define BFM_APBH_CHn_DEBUG1_RSVD1(v)                    BM_APBH_CHn_DEBUG1_RSVD1
#define BF_APBH_CHn_DEBUG1_RSVD1_V(e)                   BF_APBH_CHn_DEBUG1_RSVD1(BV_APBH_CHn_DEBUG1_RSVD1__##e)
#define BFM_APBH_CHn_DEBUG1_RSVD1_V(v)                  BM_APBH_CHn_DEBUG1_RSVD1
#define BP_APBH_CHn_DEBUG1_STATEMACHINE                 0
#define BM_APBH_CHn_DEBUG1_STATEMACHINE                 0x1f
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)              (((v) & 0x1f) << 0)
#define BFM_APBH_CHn_DEBUG1_STATEMACHINE(v)             BM_APBH_CHn_DEBUG1_STATEMACHINE
#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(e)            BF_APBH_CHn_DEBUG1_STATEMACHINE(BV_APBH_CHn_DEBUG1_STATEMACHINE__##e)
#define BFM_APBH_CHn_DEBUG1_STATEMACHINE_V(v)           BM_APBH_CHn_DEBUG1_STATEMACHINE

#endif /* __HEADERGEN_STMP3600_APBH_H__*/
