/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * imx233 version: 2.4.0
 * imx233 authors: Amaury Pouly
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_IMX233_ICOLL_H__
#define __HEADERGEN_IMX233_ICOLL_H__

#define HW_ICOLL_VECTOR                 HW(ICOLL_VECTOR)
#define HWA_ICOLL_VECTOR                (0x80000000 + 0x0)
#define HWT_ICOLL_VECTOR                HWIO_32_RW
#define HWN_ICOLL_VECTOR                ICOLL_VECTOR
#define HWI_ICOLL_VECTOR                
#define HW_ICOLL_VECTOR_SET             HW(ICOLL_VECTOR_SET)
#define HWA_ICOLL_VECTOR_SET            (HWA_ICOLL_VECTOR + 0x4)
#define HWT_ICOLL_VECTOR_SET            HWIO_32_WO
#define HWN_ICOLL_VECTOR_SET            ICOLL_VECTOR
#define HWI_ICOLL_VECTOR_SET            
#define HW_ICOLL_VECTOR_CLR             HW(ICOLL_VECTOR_CLR)
#define HWA_ICOLL_VECTOR_CLR            (HWA_ICOLL_VECTOR + 0x8)
#define HWT_ICOLL_VECTOR_CLR            HWIO_32_WO
#define HWN_ICOLL_VECTOR_CLR            ICOLL_VECTOR
#define HWI_ICOLL_VECTOR_CLR            
#define HW_ICOLL_VECTOR_TOG             HW(ICOLL_VECTOR_TOG)
#define HWA_ICOLL_VECTOR_TOG            (HWA_ICOLL_VECTOR + 0xc)
#define HWT_ICOLL_VECTOR_TOG            HWIO_32_WO
#define HWN_ICOLL_VECTOR_TOG            ICOLL_VECTOR
#define HWI_ICOLL_VECTOR_TOG            
#define BP_ICOLL_VECTOR_IRQVECTOR       2
#define BM_ICOLL_VECTOR_IRQVECTOR       0xfffffffc
#define BF_ICOLL_VECTOR_IRQVECTOR(v)    (((v) & 0x3fffffff) << 2)
#define BFM_ICOLL_VECTOR_IRQVECTOR(v)   BM_ICOLL_VECTOR_IRQVECTOR
#define BF_ICOLL_VECTOR_IRQVECTOR_V(e)  BF_ICOLL_VECTOR_IRQVECTOR(BV_ICOLL_VECTOR_IRQVECTOR__##e)
#define BFM_ICOLL_VECTOR_IRQVECTOR_V(v) BM_ICOLL_VECTOR_IRQVECTOR
#define BP_ICOLL_VECTOR_RSRVD1          0
#define BM_ICOLL_VECTOR_RSRVD1          0x3
#define BF_ICOLL_VECTOR_RSRVD1(v)       (((v) & 0x3) << 0)
#define BFM_ICOLL_VECTOR_RSRVD1(v)      BM_ICOLL_VECTOR_RSRVD1
#define BF_ICOLL_VECTOR_RSRVD1_V(e)     BF_ICOLL_VECTOR_RSRVD1(BV_ICOLL_VECTOR_RSRVD1__##e)
#define BFM_ICOLL_VECTOR_RSRVD1_V(v)    BM_ICOLL_VECTOR_RSRVD1

#define HW_ICOLL_LEVELACK                       HW(ICOLL_LEVELACK)
#define HWA_ICOLL_LEVELACK                      (0x80000000 + 0x10)
#define HWT_ICOLL_LEVELACK                      HWIO_32_RW
#define HWN_ICOLL_LEVELACK                      ICOLL_LEVELACK
#define HWI_ICOLL_LEVELACK                      
#define BP_ICOLL_LEVELACK_RSRVD1                4
#define BM_ICOLL_LEVELACK_RSRVD1                0xfffffff0
#define BF_ICOLL_LEVELACK_RSRVD1(v)             (((v) & 0xfffffff) << 4)
#define BFM_ICOLL_LEVELACK_RSRVD1(v)            BM_ICOLL_LEVELACK_RSRVD1
#define BF_ICOLL_LEVELACK_RSRVD1_V(e)           BF_ICOLL_LEVELACK_RSRVD1(BV_ICOLL_LEVELACK_RSRVD1__##e)
#define BFM_ICOLL_LEVELACK_RSRVD1_V(v)          BM_ICOLL_LEVELACK_RSRVD1
#define BP_ICOLL_LEVELACK_IRQLEVELACK           0
#define BM_ICOLL_LEVELACK_IRQLEVELACK           0xf
#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1   0x2
#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2   0x4
#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3   0x8
#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)        (((v) & 0xf) << 0)
#define BFM_ICOLL_LEVELACK_IRQLEVELACK(v)       BM_ICOLL_LEVELACK_IRQLEVELACK
#define BF_ICOLL_LEVELACK_IRQLEVELACK_V(e)      BF_ICOLL_LEVELACK_IRQLEVELACK(BV_ICOLL_LEVELACK_IRQLEVELACK__##e)
#define BFM_ICOLL_LEVELACK_IRQLEVELACK_V(v)     BM_ICOLL_LEVELACK_IRQLEVELACK

#define HW_ICOLL_CTRL                           HW(ICOLL_CTRL)
#define HWA_ICOLL_CTRL                          (0x80000000 + 0x20)
#define HWT_ICOLL_CTRL                          HWIO_32_RW
#define HWN_ICOLL_CTRL                          ICOLL_CTRL
#define HWI_ICOLL_CTRL                          
#define HW_ICOLL_CTRL_SET                       HW(ICOLL_CTRL_SET)
#define HWA_ICOLL_CTRL_SET                      (HWA_ICOLL_CTRL + 0x4)
#define HWT_ICOLL_CTRL_SET                      HWIO_32_WO
#define HWN_ICOLL_CTRL_SET                      ICOLL_CTRL
#define HWI_ICOLL_CTRL_SET                      
#define HW_ICOLL_CTRL_CLR                       HW(ICOLL_CTRL_CLR)
#define HWA_ICOLL_CTRL_CLR                      (HWA_ICOLL_CTRL + 0x8)
#define HWT_ICOLL_CTRL_CLR                      HWIO_32_WO
#define HWN_ICOLL_CTRL_CLR                      ICOLL_CTRL
#define HWI_ICOLL_CTRL_CLR                      
#define HW_ICOLL_CTRL_TOG                       HW(ICOLL_CTRL_TOG)
#define HWA_ICOLL_CTRL_TOG                      (HWA_ICOLL_CTRL + 0xc)
#define HWT_ICOLL_CTRL_TOG                      HWIO_32_WO
#define HWN_ICOLL_CTRL_TOG                      ICOLL_CTRL
#define HWI_ICOLL_CTRL_TOG                      
#define BP_ICOLL_CTRL_SFTRST                    31
#define BM_ICOLL_CTRL_SFTRST                    0x80000000
#define BV_ICOLL_CTRL_SFTRST__RUN               0x0
#define BV_ICOLL_CTRL_SFTRST__IN_RESET          0x1
#define BF_ICOLL_CTRL_SFTRST(v)                 (((v) & 0x1) << 31)
#define BFM_ICOLL_CTRL_SFTRST(v)                BM_ICOLL_CTRL_SFTRST
#define BF_ICOLL_CTRL_SFTRST_V(e)               BF_ICOLL_CTRL_SFTRST(BV_ICOLL_CTRL_SFTRST__##e)
#define BFM_ICOLL_CTRL_SFTRST_V(v)              BM_ICOLL_CTRL_SFTRST
#define BP_ICOLL_CTRL_CLKGATE                   30
#define BM_ICOLL_CTRL_CLKGATE                   0x40000000
#define BV_ICOLL_CTRL_CLKGATE__RUN              0x0
#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS        0x1
#define BF_ICOLL_CTRL_CLKGATE(v)                (((v) & 0x1) << 30)
#define BFM_ICOLL_CTRL_CLKGATE(v)               BM_ICOLL_CTRL_CLKGATE
#define BF_ICOLL_CTRL_CLKGATE_V(e)              BF_ICOLL_CTRL_CLKGATE(BV_ICOLL_CTRL_CLKGATE__##e)
#define BFM_ICOLL_CTRL_CLKGATE_V(v)             BM_ICOLL_CTRL_CLKGATE
#define BP_ICOLL_CTRL_RSRVD3                    24
#define BM_ICOLL_CTRL_RSRVD3                    0x3f000000
#define BF_ICOLL_CTRL_RSRVD3(v)                 (((v) & 0x3f) << 24)
#define BFM_ICOLL_CTRL_RSRVD3(v)                BM_ICOLL_CTRL_RSRVD3
#define BF_ICOLL_CTRL_RSRVD3_V(e)               BF_ICOLL_CTRL_RSRVD3(BV_ICOLL_CTRL_RSRVD3__##e)
#define BFM_ICOLL_CTRL_RSRVD3_V(v)              BM_ICOLL_CTRL_RSRVD3
#define BP_ICOLL_CTRL_VECTOR_PITCH              21
#define BM_ICOLL_CTRL_VECTOR_PITCH              0xe00000
#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4         0x1
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8         0x2
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12        0x3
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16        0x4
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20        0x5
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24        0x6
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28        0x7
#define BF_ICOLL_CTRL_VECTOR_PITCH(v)           (((v) & 0x7) << 21)
#define BFM_ICOLL_CTRL_VECTOR_PITCH(v)          BM_ICOLL_CTRL_VECTOR_PITCH
#define BF_ICOLL_CTRL_VECTOR_PITCH_V(e)         BF_ICOLL_CTRL_VECTOR_PITCH(BV_ICOLL_CTRL_VECTOR_PITCH__##e)
#define BFM_ICOLL_CTRL_VECTOR_PITCH_V(v)        BM_ICOLL_CTRL_VECTOR_PITCH
#define BP_ICOLL_CTRL_BYPASS_FSM                20
#define BM_ICOLL_CTRL_BYPASS_FSM                0x100000
#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL        0x0
#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS        0x1
#define BF_ICOLL_CTRL_BYPASS_FSM(v)             (((v) & 0x1) << 20)
#define BFM_ICOLL_CTRL_BYPASS_FSM(v)            BM_ICOLL_CTRL_BYPASS_FSM
#define BF_ICOLL_CTRL_BYPASS_FSM_V(e)           BF_ICOLL_CTRL_BYPASS_FSM(BV_ICOLL_CTRL_BYPASS_FSM__##e)
#define BFM_ICOLL_CTRL_BYPASS_FSM_V(v)          BM_ICOLL_CTRL_BYPASS_FSM
#define BP_ICOLL_CTRL_NO_NESTING                19
#define BM_ICOLL_CTRL_NO_NESTING                0x80000
#define BV_ICOLL_CTRL_NO_NESTING__NORMAL        0x0
#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST       0x1
#define BF_ICOLL_CTRL_NO_NESTING(v)             (((v) & 0x1) << 19)
#define BFM_ICOLL_CTRL_NO_NESTING(v)            BM_ICOLL_CTRL_NO_NESTING
#define BF_ICOLL_CTRL_NO_NESTING_V(e)           BF_ICOLL_CTRL_NO_NESTING(BV_ICOLL_CTRL_NO_NESTING__##e)
#define BFM_ICOLL_CTRL_NO_NESTING_V(v)          BM_ICOLL_CTRL_NO_NESTING
#define BP_ICOLL_CTRL_ARM_RSE_MODE              18
#define BM_ICOLL_CTRL_ARM_RSE_MODE              0x40000
#define BF_ICOLL_CTRL_ARM_RSE_MODE(v)           (((v) & 0x1) << 18)
#define BFM_ICOLL_CTRL_ARM_RSE_MODE(v)          BM_ICOLL_CTRL_ARM_RSE_MODE
#define BF_ICOLL_CTRL_ARM_RSE_MODE_V(e)         BF_ICOLL_CTRL_ARM_RSE_MODE(BV_ICOLL_CTRL_ARM_RSE_MODE__##e)
#define BFM_ICOLL_CTRL_ARM_RSE_MODE_V(v)        BM_ICOLL_CTRL_ARM_RSE_MODE
#define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE          17
#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE          0x20000
#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0
#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE  0x1
#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)       (((v) & 0x1) << 17)
#define BFM_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)      BM_ICOLL_CTRL_FIQ_FINAL_ENABLE
#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(e)     BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##e)
#define BFM_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v)    BM_ICOLL_CTRL_FIQ_FINAL_ENABLE
#define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE          16
#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE          0x10000
#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0
#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE  0x1
#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)       (((v) & 0x1) << 16)
#define BFM_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)      BM_ICOLL_CTRL_IRQ_FINAL_ENABLE
#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(e)     BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##e)
#define BFM_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v)    BM_ICOLL_CTRL_IRQ_FINAL_ENABLE
#define BP_ICOLL_CTRL_RSRVD1                    0
#define BM_ICOLL_CTRL_RSRVD1                    0xffff
#define BF_ICOLL_CTRL_RSRVD1(v)                 (((v) & 0xffff) << 0)
#define BFM_ICOLL_CTRL_RSRVD1(v)                BM_ICOLL_CTRL_RSRVD1
#define BF_ICOLL_CTRL_RSRVD1_V(e)               BF_ICOLL_CTRL_RSRVD1(BV_ICOLL_CTRL_RSRVD1__##e)
#define BFM_ICOLL_CTRL_RSRVD1_V(v)              BM_ICOLL_CTRL_RSRVD1

#define HW_ICOLL_VBASE                      HW(ICOLL_VBASE)
#define HWA_ICOLL_VBASE                     (0x80000000 + 0x40)
#define HWT_ICOLL_VBASE                     HWIO_32_RW
#define HWN_ICOLL_VBASE                     ICOLL_VBASE
#define HWI_ICOLL_VBASE                     
#define HW_ICOLL_VBASE_SET                  HW(ICOLL_VBASE_SET)
#define HWA_ICOLL_VBASE_SET                 (HWA_ICOLL_VBASE + 0x4)
#define HWT_ICOLL_VBASE_SET                 HWIO_32_WO
#define HWN_ICOLL_VBASE_SET                 ICOLL_VBASE
#define HWI_ICOLL_VBASE_SET                 
#define HW_ICOLL_VBASE_CLR                  HW(ICOLL_VBASE_CLR)
#define HWA_ICOLL_VBASE_CLR                 (HWA_ICOLL_VBASE + 0x8)
#define HWT_ICOLL_VBASE_CLR                 HWIO_32_WO
#define HWN_ICOLL_VBASE_CLR                 ICOLL_VBASE
#define HWI_ICOLL_VBASE_CLR                 
#define HW_ICOLL_VBASE_TOG                  HW(ICOLL_VBASE_TOG)
#define HWA_ICOLL_VBASE_TOG                 (HWA_ICOLL_VBASE + 0xc)
#define HWT_ICOLL_VBASE_TOG                 HWIO_32_WO
#define HWN_ICOLL_VBASE_TOG                 ICOLL_VBASE
#define HWI_ICOLL_VBASE_TOG                 
#define BP_ICOLL_VBASE_TABLE_ADDRESS        2
#define BM_ICOLL_VBASE_TABLE_ADDRESS        0xfffffffc
#define BF_ICOLL_VBASE_TABLE_ADDRESS(v)     (((v) & 0x3fffffff) << 2)
#define BFM_ICOLL_VBASE_TABLE_ADDRESS(v)    BM_ICOLL_VBASE_TABLE_ADDRESS
#define BF_ICOLL_VBASE_TABLE_ADDRESS_V(e)   BF_ICOLL_VBASE_TABLE_ADDRESS(BV_ICOLL_VBASE_TABLE_ADDRESS__##e)
#define BFM_ICOLL_VBASE_TABLE_ADDRESS_V(v)  BM_ICOLL_VBASE_TABLE_ADDRESS
#define BP_ICOLL_VBASE_RSRVD1               0
#define BM_ICOLL_VBASE_RSRVD1               0x3
#define BF_ICOLL_VBASE_RSRVD1(v)            (((v) & 0x3) << 0)
#define BFM_ICOLL_VBASE_RSRVD1(v)           BM_ICOLL_VBASE_RSRVD1
#define BF_ICOLL_VBASE_RSRVD1_V(e)          BF_ICOLL_VBASE_RSRVD1(BV_ICOLL_VBASE_RSRVD1__##e)
#define BFM_ICOLL_VBASE_RSRVD1_V(v)         BM_ICOLL_VBASE_RSRVD1

#define HW_ICOLL_STAT                       HW(ICOLL_STAT)
#define HWA_ICOLL_STAT                      (0x80000000 + 0x70)
#define HWT_ICOLL_STAT                      HWIO_32_RW
#define HWN_ICOLL_STAT                      ICOLL_STAT
#define HWI_ICOLL_STAT                      
#define BP_ICOLL_STAT_RSRVD1                7
#define BM_ICOLL_STAT_RSRVD1                0xffffff80
#define BF_ICOLL_STAT_RSRVD1(v)             (((v) & 0x1ffffff) << 7)
#define BFM_ICOLL_STAT_RSRVD1(v)            BM_ICOLL_STAT_RSRVD1
#define BF_ICOLL_STAT_RSRVD1_V(e)           BF_ICOLL_STAT_RSRVD1(BV_ICOLL_STAT_RSRVD1__##e)
#define BFM_ICOLL_STAT_RSRVD1_V(v)          BM_ICOLL_STAT_RSRVD1
#define BP_ICOLL_STAT_VECTOR_NUMBER         0
#define BM_ICOLL_STAT_VECTOR_NUMBER         0x7f
#define BF_ICOLL_STAT_VECTOR_NUMBER(v)      (((v) & 0x7f) << 0)
#define BFM_ICOLL_STAT_VECTOR_NUMBER(v)     BM_ICOLL_STAT_VECTOR_NUMBER
#define BF_ICOLL_STAT_VECTOR_NUMBER_V(e)    BF_ICOLL_STAT_VECTOR_NUMBER(BV_ICOLL_STAT_VECTOR_NUMBER__##e)
#define BFM_ICOLL_STAT_VECTOR_NUMBER_V(v)   BM_ICOLL_STAT_VECTOR_NUMBER

#define HW_ICOLL_RAWn(_n1)              HW(ICOLL_RAWn(_n1))
#define HWA_ICOLL_RAWn(_n1)             (0x80000000 + 0xa0 + (_n1) * 0x10)
#define HWT_ICOLL_RAWn(_n1)             HWIO_32_RW
#define HWN_ICOLL_RAWn(_n1)             ICOLL_RAWn
#define HWI_ICOLL_RAWn(_n1)             (_n1)
#define HW_ICOLL_RAWn_SET(_n1)          HW(ICOLL_RAWn_SET(_n1))
#define HWA_ICOLL_RAWn_SET(_n1)         (HWA_ICOLL_RAWn(_n1) + 0x4)
#define HWT_ICOLL_RAWn_SET(_n1)         HWIO_32_WO
#define HWN_ICOLL_RAWn_SET(_n1)         ICOLL_RAWn
#define HWI_ICOLL_RAWn_SET(_n1)         (_n1)
#define HW_ICOLL_RAWn_CLR(_n1)          HW(ICOLL_RAWn_CLR(_n1))
#define HWA_ICOLL_RAWn_CLR(_n1)         (HWA_ICOLL_RAWn(_n1) + 0x8)
#define HWT_ICOLL_RAWn_CLR(_n1)         HWIO_32_WO
#define HWN_ICOLL_RAWn_CLR(_n1)         ICOLL_RAWn
#define HWI_ICOLL_RAWn_CLR(_n1)         (_n1)
#define HW_ICOLL_RAWn_TOG(_n1)          HW(ICOLL_RAWn_TOG(_n1))
#define HWA_ICOLL_RAWn_TOG(_n1)         (HWA_ICOLL_RAWn(_n1) + 0xc)
#define HWT_ICOLL_RAWn_TOG(_n1)         HWIO_32_WO
#define HWN_ICOLL_RAWn_TOG(_n1)         ICOLL_RAWn
#define HWI_ICOLL_RAWn_TOG(_n1)         (_n1)
#define BP_ICOLL_RAWn_RAW_IRQS          0
#define BM_ICOLL_RAWn_RAW_IRQS          0xffffffff
#define BF_ICOLL_RAWn_RAW_IRQS(v)       (((v) & 0xffffffff) << 0)
#define BFM_ICOLL_RAWn_RAW_IRQS(v)      BM_ICOLL_RAWn_RAW_IRQS
#define BF_ICOLL_RAWn_RAW_IRQS_V(e)     BF_ICOLL_RAWn_RAW_IRQS(BV_ICOLL_RAWn_RAW_IRQS__##e)
#define BFM_ICOLL_RAWn_RAW_IRQS_V(v)    BM_ICOLL_RAWn_RAW_IRQS

#define HW_ICOLL_INTERRUPTn(_n1)                        HW(ICOLL_INTERRUPTn(_n1))
#define HWA_ICOLL_INTERRUPTn(_n1)                       (0x80000000 + 0x120 + (_n1) * 0x10)
#define HWT_ICOLL_INTERRUPTn(_n1)                       HWIO_32_RW
#define HWN_ICOLL_INTERRUPTn(_n1)                       ICOLL_INTERRUPTn
#define HWI_ICOLL_INTERRUPTn(_n1)                       (_n1)
#define HW_ICOLL_INTERRUPTn_SET(_n1)                    HW(ICOLL_INTERRUPTn_SET(_n1))
#define HWA_ICOLL_INTERRUPTn_SET(_n1)                   (HWA_ICOLL_INTERRUPTn(_n1) + 0x4)
#define HWT_ICOLL_INTERRUPTn_SET(_n1)                   HWIO_32_WO
#define HWN_ICOLL_INTERRUPTn_SET(_n1)                   ICOLL_INTERRUPTn
#define HWI_ICOLL_INTERRUPTn_SET(_n1)                   (_n1)
#define HW_ICOLL_INTERRUPTn_CLR(_n1)                    HW(ICOLL_INTERRUPTn_CLR(_n1))
#define HWA_ICOLL_INTERRUPTn_CLR(_n1)                   (HWA_ICOLL_INTERRUPTn(_n1) + 0x8)
#define HWT_ICOLL_INTERRUPTn_CLR(_n1)                   HWIO_32_WO
#define HWN_ICOLL_INTERRUPTn_CLR(_n1)                   ICOLL_INTERRUPTn
#define HWI_ICOLL_INTERRUPTn_CLR(_n1)                   (_n1)
#define HW_ICOLL_INTERRUPTn_TOG(_n1)                    HW(ICOLL_INTERRUPTn_TOG(_n1))
#define HWA_ICOLL_INTERRUPTn_TOG(_n1)                   (HWA_ICOLL_INTERRUPTn(_n1) + 0xc)
#define HWT_ICOLL_INTERRUPTn_TOG(_n1)                   HWIO_32_WO
#define HWN_ICOLL_INTERRUPTn_TOG(_n1)                   ICOLL_INTERRUPTn
#define HWI_ICOLL_INTERRUPTn_TOG(_n1)                   (_n1)
#define BP_ICOLL_INTERRUPTn_RSRVD1                      5
#define BM_ICOLL_INTERRUPTn_RSRVD1                      0xffffffe0
#define BF_ICOLL_INTERRUPTn_RSRVD1(v)                   (((v) & 0x7ffffff) << 5)
#define BFM_ICOLL_INTERRUPTn_RSRVD1(v)                  BM_ICOLL_INTERRUPTn_RSRVD1
#define BF_ICOLL_INTERRUPTn_RSRVD1_V(e)                 BF_ICOLL_INTERRUPTn_RSRVD1(BV_ICOLL_INTERRUPTn_RSRVD1__##e)
#define BFM_ICOLL_INTERRUPTn_RSRVD1_V(v)                BM_ICOLL_INTERRUPTn_RSRVD1
#define BP_ICOLL_INTERRUPTn_ENFIQ                       4
#define BM_ICOLL_INTERRUPTn_ENFIQ                       0x10
#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE              0x0
#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE               0x1
#define BF_ICOLL_INTERRUPTn_ENFIQ(v)                    (((v) & 0x1) << 4)
#define BFM_ICOLL_INTERRUPTn_ENFIQ(v)                   BM_ICOLL_INTERRUPTn_ENFIQ
#define BF_ICOLL_INTERRUPTn_ENFIQ_V(e)                  BF_ICOLL_INTERRUPTn_ENFIQ(BV_ICOLL_INTERRUPTn_ENFIQ__##e)
#define BFM_ICOLL_INTERRUPTn_ENFIQ_V(v)                 BM_ICOLL_INTERRUPTn_ENFIQ
#define BP_ICOLL_INTERRUPTn_SOFTIRQ                     3
#define BM_ICOLL_INTERRUPTn_SOFTIRQ                     0x8
#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT       0x0
#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT    0x1
#define BF_ICOLL_INTERRUPTn_SOFTIRQ(v)                  (((v) & 0x1) << 3)
#define BFM_ICOLL_INTERRUPTn_SOFTIRQ(v)                 BM_ICOLL_INTERRUPTn_SOFTIRQ
#define BF_ICOLL_INTERRUPTn_SOFTIRQ_V(e)                BF_ICOLL_INTERRUPTn_SOFTIRQ(BV_ICOLL_INTERRUPTn_SOFTIRQ__##e)
#define BFM_ICOLL_INTERRUPTn_SOFTIRQ_V(v)               BM_ICOLL_INTERRUPTn_SOFTIRQ
#define BP_ICOLL_INTERRUPTn_ENABLE                      2
#define BM_ICOLL_INTERRUPTn_ENABLE                      0x4
#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE             0x0
#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE              0x1
#define BF_ICOLL_INTERRUPTn_ENABLE(v)                   (((v) & 0x1) << 2)
#define BFM_ICOLL_INTERRUPTn_ENABLE(v)                  BM_ICOLL_INTERRUPTn_ENABLE
#define BF_ICOLL_INTERRUPTn_ENABLE_V(e)                 BF_ICOLL_INTERRUPTn_ENABLE(BV_ICOLL_INTERRUPTn_ENABLE__##e)
#define BFM_ICOLL_INTERRUPTn_ENABLE_V(v)                BM_ICOLL_INTERRUPTn_ENABLE
#define BP_ICOLL_INTERRUPTn_PRIORITY                    0
#define BM_ICOLL_INTERRUPTn_PRIORITY                    0x3
#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0            0x0
#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1            0x1
#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2            0x2
#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3            0x3
#define BF_ICOLL_INTERRUPTn_PRIORITY(v)                 (((v) & 0x3) << 0)
#define BFM_ICOLL_INTERRUPTn_PRIORITY(v)                BM_ICOLL_INTERRUPTn_PRIORITY
#define BF_ICOLL_INTERRUPTn_PRIORITY_V(e)               BF_ICOLL_INTERRUPTn_PRIORITY(BV_ICOLL_INTERRUPTn_PRIORITY__##e)
#define BFM_ICOLL_INTERRUPTn_PRIORITY_V(v)              BM_ICOLL_INTERRUPTn_PRIORITY

#define HW_ICOLL_DEBUG                              HW(ICOLL_DEBUG)
#define HWA_ICOLL_DEBUG                             (0x80000000 + 0x1120)
#define HWT_ICOLL_DEBUG                             HWIO_32_RW
#define HWN_ICOLL_DEBUG                             ICOLL_DEBUG
#define HWI_ICOLL_DEBUG                             
#define HW_ICOLL_DEBUG_SET                          HW(ICOLL_DEBUG_SET)
#define HWA_ICOLL_DEBUG_SET                         (HWA_ICOLL_DEBUG + 0x4)
#define HWT_ICOLL_DEBUG_SET                         HWIO_32_WO
#define HWN_ICOLL_DEBUG_SET                         ICOLL_DEBUG
#define HWI_ICOLL_DEBUG_SET                         
#define HW_ICOLL_DEBUG_CLR                          HW(ICOLL_DEBUG_CLR)
#define HWA_ICOLL_DEBUG_CLR                         (HWA_ICOLL_DEBUG + 0x8)
#define HWT_ICOLL_DEBUG_CLR                         HWIO_32_WO
#define HWN_ICOLL_DEBUG_CLR                         ICOLL_DEBUG
#define HWI_ICOLL_DEBUG_CLR                         
#define HW_ICOLL_DEBUG_TOG                          HW(ICOLL_DEBUG_TOG)
#define HWA_ICOLL_DEBUG_TOG                         (HWA_ICOLL_DEBUG + 0xc)
#define HWT_ICOLL_DEBUG_TOG                         HWIO_32_WO
#define HWN_ICOLL_DEBUG_TOG                         ICOLL_DEBUG
#define HWI_ICOLL_DEBUG_TOG                         
#define BP_ICOLL_DEBUG_INSERVICE                    28
#define BM_ICOLL_DEBUG_INSERVICE                    0xf0000000
#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0            0x1
#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1            0x2
#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2            0x4
#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3            0x8
#define BF_ICOLL_DEBUG_INSERVICE(v)                 (((v) & 0xf) << 28)
#define BFM_ICOLL_DEBUG_INSERVICE(v)                BM_ICOLL_DEBUG_INSERVICE
#define BF_ICOLL_DEBUG_INSERVICE_V(e)               BF_ICOLL_DEBUG_INSERVICE(BV_ICOLL_DEBUG_INSERVICE__##e)
#define BFM_ICOLL_DEBUG_INSERVICE_V(v)              BM_ICOLL_DEBUG_INSERVICE
#define BP_ICOLL_DEBUG_LEVEL_REQUESTS               24
#define BM_ICOLL_DEBUG_LEVEL_REQUESTS               0xf000000
#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0       0x1
#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1       0x2
#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2       0x4
#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3       0x8
#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)            (((v) & 0xf) << 24)
#define BFM_ICOLL_DEBUG_LEVEL_REQUESTS(v)           BM_ICOLL_DEBUG_LEVEL_REQUESTS
#define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(e)          BF_ICOLL_DEBUG_LEVEL_REQUESTS(BV_ICOLL_DEBUG_LEVEL_REQUESTS__##e)
#define BFM_ICOLL_DEBUG_LEVEL_REQUESTS_V(v)         BM_ICOLL_DEBUG_LEVEL_REQUESTS
#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL            20
#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL            0xf00000
#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0    0x1
#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1    0x2
#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2    0x4
#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3    0x8
#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)         (((v) & 0xf) << 20)
#define BFM_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)        BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL
#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(e)       BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##e)
#define BFM_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v)      BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL
#define BP_ICOLL_DEBUG_RSRVD2                       18
#define BM_ICOLL_DEBUG_RSRVD2                       0xc0000
#define BF_ICOLL_DEBUG_RSRVD2(v)                    (((v) & 0x3) << 18)
#define BFM_ICOLL_DEBUG_RSRVD2(v)                   BM_ICOLL_DEBUG_RSRVD2
#define BF_ICOLL_DEBUG_RSRVD2_V(e)                  BF_ICOLL_DEBUG_RSRVD2(BV_ICOLL_DEBUG_RSRVD2__##e)
#define BFM_ICOLL_DEBUG_RSRVD2_V(v)                 BM_ICOLL_DEBUG_RSRVD2
#define BP_ICOLL_DEBUG_FIQ                          17
#define BM_ICOLL_DEBUG_FIQ                          0x20000
#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED        0x0
#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED           0x1
#define BF_ICOLL_DEBUG_FIQ(v)                       (((v) & 0x1) << 17)
#define BFM_ICOLL_DEBUG_FIQ(v)                      BM_ICOLL_DEBUG_FIQ
#define BF_ICOLL_DEBUG_FIQ_V(e)                     BF_ICOLL_DEBUG_FIQ(BV_ICOLL_DEBUG_FIQ__##e)
#define BFM_ICOLL_DEBUG_FIQ_V(v)                    BM_ICOLL_DEBUG_FIQ
#define BP_ICOLL_DEBUG_IRQ                          16
#define BM_ICOLL_DEBUG_IRQ                          0x10000
#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED        0x0
#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED           0x1
#define BF_ICOLL_DEBUG_IRQ(v)                       (((v) & 0x1) << 16)
#define BFM_ICOLL_DEBUG_IRQ(v)                      BM_ICOLL_DEBUG_IRQ
#define BF_ICOLL_DEBUG_IRQ_V(e)                     BF_ICOLL_DEBUG_IRQ(BV_ICOLL_DEBUG_IRQ__##e)
#define BFM_ICOLL_DEBUG_IRQ_V(v)                    BM_ICOLL_DEBUG_IRQ
#define BP_ICOLL_DEBUG_RSRVD1                       10
#define BM_ICOLL_DEBUG_RSRVD1                       0xfc00
#define BF_ICOLL_DEBUG_RSRVD1(v)                    (((v) & 0x3f) << 10)
#define BFM_ICOLL_DEBUG_RSRVD1(v)                   BM_ICOLL_DEBUG_RSRVD1
#define BF_ICOLL_DEBUG_RSRVD1_V(e)                  BF_ICOLL_DEBUG_RSRVD1(BV_ICOLL_DEBUG_RSRVD1__##e)
#define BFM_ICOLL_DEBUG_RSRVD1_V(v)                 BM_ICOLL_DEBUG_RSRVD1
#define BP_ICOLL_DEBUG_VECTOR_FSM                   0
#define BM_ICOLL_DEBUG_VECTOR_FSM                   0x3ff
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x0
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x1
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x2
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x4
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x8
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x10
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
#define BF_ICOLL_DEBUG_VECTOR_FSM(v)                (((v) & 0x3ff) << 0)
#define BFM_ICOLL_DEBUG_VECTOR_FSM(v)               BM_ICOLL_DEBUG_VECTOR_FSM
#define BF_ICOLL_DEBUG_VECTOR_FSM_V(e)              BF_ICOLL_DEBUG_VECTOR_FSM(BV_ICOLL_DEBUG_VECTOR_FSM__##e)
#define BFM_ICOLL_DEBUG_VECTOR_FSM_V(v)             BM_ICOLL_DEBUG_VECTOR_FSM

#define HW_ICOLL_DBGREAD0               HW(ICOLL_DBGREAD0)
#define HWA_ICOLL_DBGREAD0              (0x80000000 + 0x1130)
#define HWT_ICOLL_DBGREAD0              HWIO_32_RW
#define HWN_ICOLL_DBGREAD0              ICOLL_DBGREAD0
#define HWI_ICOLL_DBGREAD0              
#define HW_ICOLL_DBGREAD0_SET           HW(ICOLL_DBGREAD0_SET)
#define HWA_ICOLL_DBGREAD0_SET          (HWA_ICOLL_DBGREAD0 + 0x4)
#define HWT_ICOLL_DBGREAD0_SET          HWIO_32_WO
#define HWN_ICOLL_DBGREAD0_SET          ICOLL_DBGREAD0
#define HWI_ICOLL_DBGREAD0_SET          
#define HW_ICOLL_DBGREAD0_CLR           HW(ICOLL_DBGREAD0_CLR)
#define HWA_ICOLL_DBGREAD0_CLR          (HWA_ICOLL_DBGREAD0 + 0x8)
#define HWT_ICOLL_DBGREAD0_CLR          HWIO_32_WO
#define HWN_ICOLL_DBGREAD0_CLR          ICOLL_DBGREAD0
#define HWI_ICOLL_DBGREAD0_CLR          
#define HW_ICOLL_DBGREAD0_TOG           HW(ICOLL_DBGREAD0_TOG)
#define HWA_ICOLL_DBGREAD0_TOG          (HWA_ICOLL_DBGREAD0 + 0xc)
#define HWT_ICOLL_DBGREAD0_TOG          HWIO_32_WO
#define HWN_ICOLL_DBGREAD0_TOG          ICOLL_DBGREAD0
#define HWI_ICOLL_DBGREAD0_TOG          
#define BP_ICOLL_DBGREAD0_VALUE         0
#define BM_ICOLL_DBGREAD0_VALUE         0xffffffff
#define BF_ICOLL_DBGREAD0_VALUE(v)      (((v) & 0xffffffff) << 0)
#define BFM_ICOLL_DBGREAD0_VALUE(v)     BM_ICOLL_DBGREAD0_VALUE
#define BF_ICOLL_DBGREAD0_VALUE_V(e)    BF_ICOLL_DBGREAD0_VALUE(BV_ICOLL_DBGREAD0_VALUE__##e)
#define BFM_ICOLL_DBGREAD0_VALUE_V(v)   BM_ICOLL_DBGREAD0_VALUE

#define HW_ICOLL_DBGREAD1               HW(ICOLL_DBGREAD1)
#define HWA_ICOLL_DBGREAD1              (0x80000000 + 0x1140)
#define HWT_ICOLL_DBGREAD1              HWIO_32_RW
#define HWN_ICOLL_DBGREAD1              ICOLL_DBGREAD1
#define HWI_ICOLL_DBGREAD1              
#define HW_ICOLL_DBGREAD1_SET           HW(ICOLL_DBGREAD1_SET)
#define HWA_ICOLL_DBGREAD1_SET          (HWA_ICOLL_DBGREAD1 + 0x4)
#define HWT_ICOLL_DBGREAD1_SET          HWIO_32_WO
#define HWN_ICOLL_DBGREAD1_SET          ICOLL_DBGREAD1
#define HWI_ICOLL_DBGREAD1_SET          
#define HW_ICOLL_DBGREAD1_CLR           HW(ICOLL_DBGREAD1_CLR)
#define HWA_ICOLL_DBGREAD1_CLR          (HWA_ICOLL_DBGREAD1 + 0x8)
#define HWT_ICOLL_DBGREAD1_CLR          HWIO_32_WO
#define HWN_ICOLL_DBGREAD1_CLR          ICOLL_DBGREAD1
#define HWI_ICOLL_DBGREAD1_CLR          
#define HW_ICOLL_DBGREAD1_TOG           HW(ICOLL_DBGREAD1_TOG)
#define HWA_ICOLL_DBGREAD1_TOG          (HWA_ICOLL_DBGREAD1 + 0xc)
#define HWT_ICOLL_DBGREAD1_TOG          HWIO_32_WO
#define HWN_ICOLL_DBGREAD1_TOG          ICOLL_DBGREAD1
#define HWI_ICOLL_DBGREAD1_TOG          
#define BP_ICOLL_DBGREAD1_VALUE         0
#define BM_ICOLL_DBGREAD1_VALUE         0xffffffff
#define BF_ICOLL_DBGREAD1_VALUE(v)      (((v) & 0xffffffff) << 0)
#define BFM_ICOLL_DBGREAD1_VALUE(v)     BM_ICOLL_DBGREAD1_VALUE
#define BF_ICOLL_DBGREAD1_VALUE_V(e)    BF_ICOLL_DBGREAD1_VALUE(BV_ICOLL_DBGREAD1_VALUE__##e)
#define BFM_ICOLL_DBGREAD1_VALUE_V(v)   BM_ICOLL_DBGREAD1_VALUE

#define HW_ICOLL_DBGFLAG                HW(ICOLL_DBGFLAG)
#define HWA_ICOLL_DBGFLAG               (0x80000000 + 0x1150)
#define HWT_ICOLL_DBGFLAG               HWIO_32_RW
#define HWN_ICOLL_DBGFLAG               ICOLL_DBGFLAG
#define HWI_ICOLL_DBGFLAG               
#define HW_ICOLL_DBGFLAG_SET            HW(ICOLL_DBGFLAG_SET)
#define HWA_ICOLL_DBGFLAG_SET           (HWA_ICOLL_DBGFLAG + 0x4)
#define HWT_ICOLL_DBGFLAG_SET           HWIO_32_WO
#define HWN_ICOLL_DBGFLAG_SET           ICOLL_DBGFLAG
#define HWI_ICOLL_DBGFLAG_SET           
#define HW_ICOLL_DBGFLAG_CLR            HW(ICOLL_DBGFLAG_CLR)
#define HWA_ICOLL_DBGFLAG_CLR           (HWA_ICOLL_DBGFLAG + 0x8)
#define HWT_ICOLL_DBGFLAG_CLR           HWIO_32_WO
#define HWN_ICOLL_DBGFLAG_CLR           ICOLL_DBGFLAG
#define HWI_ICOLL_DBGFLAG_CLR           
#define HW_ICOLL_DBGFLAG_TOG            HW(ICOLL_DBGFLAG_TOG)
#define HWA_ICOLL_DBGFLAG_TOG           (HWA_ICOLL_DBGFLAG + 0xc)
#define HWT_ICOLL_DBGFLAG_TOG           HWIO_32_WO
#define HWN_ICOLL_DBGFLAG_TOG           ICOLL_DBGFLAG
#define HWI_ICOLL_DBGFLAG_TOG           
#define BP_ICOLL_DBGFLAG_RSRVD1         16
#define BM_ICOLL_DBGFLAG_RSRVD1         0xffff0000
#define BF_ICOLL_DBGFLAG_RSRVD1(v)      (((v) & 0xffff) << 16)
#define BFM_ICOLL_DBGFLAG_RSRVD1(v)     BM_ICOLL_DBGFLAG_RSRVD1
#define BF_ICOLL_DBGFLAG_RSRVD1_V(e)    BF_ICOLL_DBGFLAG_RSRVD1(BV_ICOLL_DBGFLAG_RSRVD1__##e)
#define BFM_ICOLL_DBGFLAG_RSRVD1_V(v)   BM_ICOLL_DBGFLAG_RSRVD1
#define BP_ICOLL_DBGFLAG_FLAG           0
#define BM_ICOLL_DBGFLAG_FLAG           0xffff
#define BF_ICOLL_DBGFLAG_FLAG(v)        (((v) & 0xffff) << 0)
#define BFM_ICOLL_DBGFLAG_FLAG(v)       BM_ICOLL_DBGFLAG_FLAG
#define BF_ICOLL_DBGFLAG_FLAG_V(e)      BF_ICOLL_DBGFLAG_FLAG(BV_ICOLL_DBGFLAG_FLAG__##e)
#define BFM_ICOLL_DBGFLAG_FLAG_V(v)     BM_ICOLL_DBGFLAG_FLAG

#define HW_ICOLL_DBGREQUESTn(_n1)       HW(ICOLL_DBGREQUESTn(_n1))
#define HWA_ICOLL_DBGREQUESTn(_n1)      (0x80000000 + 0x1160 + (_n1) * 0x10)
#define HWT_ICOLL_DBGREQUESTn(_n1)      HWIO_32_RW
#define HWN_ICOLL_DBGREQUESTn(_n1)      ICOLL_DBGREQUESTn
#define HWI_ICOLL_DBGREQUESTn(_n1)      (_n1)
#define HW_ICOLL_DBGREQUESTn_SET(_n1)   HW(ICOLL_DBGREQUESTn_SET(_n1))
#define HWA_ICOLL_DBGREQUESTn_SET(_n1)  (HWA_ICOLL_DBGREQUESTn(_n1) + 0x4)
#define HWT_ICOLL_DBGREQUESTn_SET(_n1)  HWIO_32_WO
#define HWN_ICOLL_DBGREQUESTn_SET(_n1)  ICOLL_DBGREQUESTn
#define HWI_ICOLL_DBGREQUESTn_SET(_n1)  (_n1)
#define HW_ICOLL_DBGREQUESTn_CLR(_n1)   HW(ICOLL_DBGREQUESTn_CLR(_n1))
#define HWA_ICOLL_DBGREQUESTn_CLR(_n1)  (HWA_ICOLL_DBGREQUESTn(_n1) + 0x8)
#define HWT_ICOLL_DBGREQUESTn_CLR(_n1)  HWIO_32_WO
#define HWN_ICOLL_DBGREQUESTn_CLR(_n1)  ICOLL_DBGREQUESTn
#define HWI_ICOLL_DBGREQUESTn_CLR(_n1)  (_n1)
#define HW_ICOLL_DBGREQUESTn_TOG(_n1)   HW(ICOLL_DBGREQUESTn_TOG(_n1))
#define HWA_ICOLL_DBGREQUESTn_TOG(_n1)  (HWA_ICOLL_DBGREQUESTn(_n1) + 0xc)
#define HWT_ICOLL_DBGREQUESTn_TOG(_n1)  HWIO_32_WO
#define HWN_ICOLL_DBGREQUESTn_TOG(_n1)  ICOLL_DBGREQUESTn
#define HWI_ICOLL_DBGREQUESTn_TOG(_n1)  (_n1)
#define BP_ICOLL_DBGREQUESTn_BITS       0
#define BM_ICOLL_DBGREQUESTn_BITS       0xffffffff
#define BF_ICOLL_DBGREQUESTn_BITS(v)    (((v) & 0xffffffff) << 0)
#define BFM_ICOLL_DBGREQUESTn_BITS(v)   BM_ICOLL_DBGREQUESTn_BITS
#define BF_ICOLL_DBGREQUESTn_BITS_V(e)  BF_ICOLL_DBGREQUESTn_BITS(BV_ICOLL_DBGREQUESTn_BITS__##e)
#define BFM_ICOLL_DBGREQUESTn_BITS_V(v) BM_ICOLL_DBGREQUESTn_BITS

#define HW_ICOLL_VERSION                HW(ICOLL_VERSION)
#define HWA_ICOLL_VERSION               (0x80000000 + 0x11e0)
#define HWT_ICOLL_VERSION               HWIO_32_RW
#define HWN_ICOLL_VERSION               ICOLL_VERSION
#define HWI_ICOLL_VERSION               
#define BP_ICOLL_VERSION_MAJOR          24
#define BM_ICOLL_VERSION_MAJOR          0xff000000
#define BF_ICOLL_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
#define BFM_ICOLL_VERSION_MAJOR(v)      BM_ICOLL_VERSION_MAJOR
#define BF_ICOLL_VERSION_MAJOR_V(e)     BF_ICOLL_VERSION_MAJOR(BV_ICOLL_VERSION_MAJOR__##e)
#define BFM_ICOLL_VERSION_MAJOR_V(v)    BM_ICOLL_VERSION_MAJOR
#define BP_ICOLL_VERSION_MINOR          16
#define BM_ICOLL_VERSION_MINOR          0xff0000
#define BF_ICOLL_VERSION_MINOR(v)       (((v) & 0xff) << 16)
#define BFM_ICOLL_VERSION_MINOR(v)      BM_ICOLL_VERSION_MINOR
#define BF_ICOLL_VERSION_MINOR_V(e)     BF_ICOLL_VERSION_MINOR(BV_ICOLL_VERSION_MINOR__##e)
#define BFM_ICOLL_VERSION_MINOR_V(v)    BM_ICOLL_VERSION_MINOR
#define BP_ICOLL_VERSION_STEP           0
#define BM_ICOLL_VERSION_STEP           0xffff
#define BF_ICOLL_VERSION_STEP(v)        (((v) & 0xffff) << 0)
#define BFM_ICOLL_VERSION_STEP(v)       BM_ICOLL_VERSION_STEP
#define BF_ICOLL_VERSION_STEP_V(e)      BF_ICOLL_VERSION_STEP(BV_ICOLL_VERSION_STEP__##e)
#define BFM_ICOLL_VERSION_STEP_V(v)     BM_ICOLL_VERSION_STEP

#endif /* __HEADERGEN_IMX233_ICOLL_H__*/
