/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * stmp3700 version: 2.4.0
 * stmp3700 authors: Amaury Pouly
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_STMP3700_DRAM_H__
#define __HEADERGEN_STMP3700_DRAM_H__

#define HW_DRAM_CTL00                           HW(DRAM_CTL00)
#define HWA_DRAM_CTL00                          (0x800e0000 + 0x0)
#define HWT_DRAM_CTL00                          HWIO_32_RW
#define HWN_DRAM_CTL00                          DRAM_CTL00
#define HWI_DRAM_CTL00                          
#define BP_DRAM_CTL00_AHB0_W_PRIORITY           24
#define BM_DRAM_CTL00_AHB0_W_PRIORITY           0x1000000
#define BF_DRAM_CTL00_AHB0_W_PRIORITY(v)        (((v) & 0x1) << 24)
#define BFM_DRAM_CTL00_AHB0_W_PRIORITY(v)       BM_DRAM_CTL00_AHB0_W_PRIORITY
#define BF_DRAM_CTL00_AHB0_W_PRIORITY_V(e)      BF_DRAM_CTL00_AHB0_W_PRIORITY(BV_DRAM_CTL00_AHB0_W_PRIORITY__##e)
#define BFM_DRAM_CTL00_AHB0_W_PRIORITY_V(v)     BM_DRAM_CTL00_AHB0_W_PRIORITY
#define BP_DRAM_CTL00_AHB0_R_PRIORITY           16
#define BM_DRAM_CTL00_AHB0_R_PRIORITY           0x10000
#define BF_DRAM_CTL00_AHB0_R_PRIORITY(v)        (((v) & 0x1) << 16)
#define BFM_DRAM_CTL00_AHB0_R_PRIORITY(v)       BM_DRAM_CTL00_AHB0_R_PRIORITY
#define BF_DRAM_CTL00_AHB0_R_PRIORITY_V(e)      BF_DRAM_CTL00_AHB0_R_PRIORITY(BV_DRAM_CTL00_AHB0_R_PRIORITY__##e)
#define BFM_DRAM_CTL00_AHB0_R_PRIORITY_V(v)     BM_DRAM_CTL00_AHB0_R_PRIORITY
#define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG        8
#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG        0x100
#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v)     (((v) & 0x1) << 8)
#define BFM_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v)    BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG
#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(BV_DRAM_CTL00_AHB0_FIFO_TYPE_REG__##e)
#define BFM_DRAM_CTL00_AHB0_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG
#define BP_DRAM_CTL00_ADDR_CMP_EN               0
#define BM_DRAM_CTL00_ADDR_CMP_EN               0x1
#define BF_DRAM_CTL00_ADDR_CMP_EN(v)            (((v) & 0x1) << 0)
#define BFM_DRAM_CTL00_ADDR_CMP_EN(v)           BM_DRAM_CTL00_ADDR_CMP_EN
#define BF_DRAM_CTL00_ADDR_CMP_EN_V(e)          BF_DRAM_CTL00_ADDR_CMP_EN(BV_DRAM_CTL00_ADDR_CMP_EN__##e)
#define BFM_DRAM_CTL00_ADDR_CMP_EN_V(v)         BM_DRAM_CTL00_ADDR_CMP_EN

#define HW_DRAM_CTL01                           HW(DRAM_CTL01)
#define HWA_DRAM_CTL01                          (0x800e0000 + 0x4)
#define HWT_DRAM_CTL01                          HWIO_32_RW
#define HWN_DRAM_CTL01                          DRAM_CTL01
#define HWI_DRAM_CTL01                          
#define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG        24
#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG        0x1000000
#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v)     (((v) & 0x1) << 24)
#define BFM_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v)    BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG
#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(BV_DRAM_CTL01_AHB2_FIFO_TYPE_REG__##e)
#define BFM_DRAM_CTL01_AHB2_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG
#define BP_DRAM_CTL01_AHB1_W_PRIORITY           16
#define BM_DRAM_CTL01_AHB1_W_PRIORITY           0x10000
#define BF_DRAM_CTL01_AHB1_W_PRIORITY(v)        (((v) & 0x1) << 16)
#define BFM_DRAM_CTL01_AHB1_W_PRIORITY(v)       BM_DRAM_CTL01_AHB1_W_PRIORITY
#define BF_DRAM_CTL01_AHB1_W_PRIORITY_V(e)      BF_DRAM_CTL01_AHB1_W_PRIORITY(BV_DRAM_CTL01_AHB1_W_PRIORITY__##e)
#define BFM_DRAM_CTL01_AHB1_W_PRIORITY_V(v)     BM_DRAM_CTL01_AHB1_W_PRIORITY
#define BP_DRAM_CTL01_AHB1_R_PRIORITY           8
#define BM_DRAM_CTL01_AHB1_R_PRIORITY           0x100
#define BF_DRAM_CTL01_AHB1_R_PRIORITY(v)        (((v) & 0x1) << 8)
#define BFM_DRAM_CTL01_AHB1_R_PRIORITY(v)       BM_DRAM_CTL01_AHB1_R_PRIORITY
#define BF_DRAM_CTL01_AHB1_R_PRIORITY_V(e)      BF_DRAM_CTL01_AHB1_R_PRIORITY(BV_DRAM_CTL01_AHB1_R_PRIORITY__##e)
#define BFM_DRAM_CTL01_AHB1_R_PRIORITY_V(v)     BM_DRAM_CTL01_AHB1_R_PRIORITY
#define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG        0
#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG        0x1
#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v)     (((v) & 0x1) << 0)
#define BFM_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v)    BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG
#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(BV_DRAM_CTL01_AHB1_FIFO_TYPE_REG__##e)
#define BFM_DRAM_CTL01_AHB1_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG

#define HW_DRAM_CTL02                           HW(DRAM_CTL02)
#define HWA_DRAM_CTL02                          (0x800e0000 + 0x8)
#define HWT_DRAM_CTL02                          HWIO_32_RW
#define HWN_DRAM_CTL02                          DRAM_CTL02
#define HWI_DRAM_CTL02                          
#define BP_DRAM_CTL02_AHB3_R_PRIORITY           24
#define BM_DRAM_CTL02_AHB3_R_PRIORITY           0x1000000
#define BF_DRAM_CTL02_AHB3_R_PRIORITY(v)        (((v) & 0x1) << 24)
#define BFM_DRAM_CTL02_AHB3_R_PRIORITY(v)       BM_DRAM_CTL02_AHB3_R_PRIORITY
#define BF_DRAM_CTL02_AHB3_R_PRIORITY_V(e)      BF_DRAM_CTL02_AHB3_R_PRIORITY(BV_DRAM_CTL02_AHB3_R_PRIORITY__##e)
#define BFM_DRAM_CTL02_AHB3_R_PRIORITY_V(v)     BM_DRAM_CTL02_AHB3_R_PRIORITY
#define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG        16
#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG        0x10000
#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v)     (((v) & 0x1) << 16)
#define BFM_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v)    BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG
#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG_V(e)   BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(BV_DRAM_CTL02_AHB3_FIFO_TYPE_REG__##e)
#define BFM_DRAM_CTL02_AHB3_FIFO_TYPE_REG_V(v)  BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG
#define BP_DRAM_CTL02_AHB2_W_PRIORITY           8
#define BM_DRAM_CTL02_AHB2_W_PRIORITY           0x100
#define BF_DRAM_CTL02_AHB2_W_PRIORITY(v)        (((v) & 0x1) << 8)
#define BFM_DRAM_CTL02_AHB2_W_PRIORITY(v)       BM_DRAM_CTL02_AHB2_W_PRIORITY
#define BF_DRAM_CTL02_AHB2_W_PRIORITY_V(e)      BF_DRAM_CTL02_AHB2_W_PRIORITY(BV_DRAM_CTL02_AHB2_W_PRIORITY__##e)
#define BFM_DRAM_CTL02_AHB2_W_PRIORITY_V(v)     BM_DRAM_CTL02_AHB2_W_PRIORITY
#define BP_DRAM_CTL02_AHB2_R_PRIORITY           0
#define BM_DRAM_CTL02_AHB2_R_PRIORITY           0x1
#define BF_DRAM_CTL02_AHB2_R_PRIORITY(v)        (((v) & 0x1) << 0)
#define BFM_DRAM_CTL02_AHB2_R_PRIORITY(v)       BM_DRAM_CTL02_AHB2_R_PRIORITY
#define BF_DRAM_CTL02_AHB2_R_PRIORITY_V(e)      BF_DRAM_CTL02_AHB2_R_PRIORITY(BV_DRAM_CTL02_AHB2_R_PRIORITY__##e)
#define BFM_DRAM_CTL02_AHB2_R_PRIORITY_V(v)     BM_DRAM_CTL02_AHB2_R_PRIORITY

#define HW_DRAM_CTL03                           HW(DRAM_CTL03)
#define HWA_DRAM_CTL03                          (0x800e0000 + 0xc)
#define HWT_DRAM_CTL03                          HWIO_32_RW
#define HWN_DRAM_CTL03                          DRAM_CTL03
#define HWI_DRAM_CTL03                          
#define BP_DRAM_CTL03_AUTO_REFRESH_MODE         24
#define BM_DRAM_CTL03_AUTO_REFRESH_MODE         0x1000000
#define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v)      (((v) & 0x1) << 24)
#define BFM_DRAM_CTL03_AUTO_REFRESH_MODE(v)     BM_DRAM_CTL03_AUTO_REFRESH_MODE
#define BF_DRAM_CTL03_AUTO_REFRESH_MODE_V(e)    BF_DRAM_CTL03_AUTO_REFRESH_MODE(BV_DRAM_CTL03_AUTO_REFRESH_MODE__##e)
#define BFM_DRAM_CTL03_AUTO_REFRESH_MODE_V(v)   BM_DRAM_CTL03_AUTO_REFRESH_MODE
#define BP_DRAM_CTL03_AREFRESH                  16
#define BM_DRAM_CTL03_AREFRESH                  0x10000
#define BF_DRAM_CTL03_AREFRESH(v)               (((v) & 0x1) << 16)
#define BFM_DRAM_CTL03_AREFRESH(v)              BM_DRAM_CTL03_AREFRESH
#define BF_DRAM_CTL03_AREFRESH_V(e)             BF_DRAM_CTL03_AREFRESH(BV_DRAM_CTL03_AREFRESH__##e)
#define BFM_DRAM_CTL03_AREFRESH_V(v)            BM_DRAM_CTL03_AREFRESH
#define BP_DRAM_CTL03_AP                        8
#define BM_DRAM_CTL03_AP                        0x100
#define BF_DRAM_CTL03_AP(v)                     (((v) & 0x1) << 8)
#define BFM_DRAM_CTL03_AP(v)                    BM_DRAM_CTL03_AP
#define BF_DRAM_CTL03_AP_V(e)                   BF_DRAM_CTL03_AP(BV_DRAM_CTL03_AP__##e)
#define BFM_DRAM_CTL03_AP_V(v)                  BM_DRAM_CTL03_AP
#define BP_DRAM_CTL03_AHB3_W_PRIORITY           0
#define BM_DRAM_CTL03_AHB3_W_PRIORITY           0x1
#define BF_DRAM_CTL03_AHB3_W_PRIORITY(v)        (((v) & 0x1) << 0)
#define BFM_DRAM_CTL03_AHB3_W_PRIORITY(v)       BM_DRAM_CTL03_AHB3_W_PRIORITY
#define BF_DRAM_CTL03_AHB3_W_PRIORITY_V(e)      BF_DRAM_CTL03_AHB3_W_PRIORITY(BV_DRAM_CTL03_AHB3_W_PRIORITY__##e)
#define BFM_DRAM_CTL03_AHB3_W_PRIORITY_V(v)     BM_DRAM_CTL03_AHB3_W_PRIORITY

#define HW_DRAM_CTL04                       HW(DRAM_CTL04)
#define HWA_DRAM_CTL04                      (0x800e0000 + 0x10)
#define HWT_DRAM_CTL04                      HWIO_32_RW
#define HWN_DRAM_CTL04                      DRAM_CTL04
#define HWI_DRAM_CTL04                      
#define BP_DRAM_CTL04_DLL_BYPASS_MODE       24
#define BM_DRAM_CTL04_DLL_BYPASS_MODE       0x1000000
#define BF_DRAM_CTL04_DLL_BYPASS_MODE(v)    (((v) & 0x1) << 24)
#define BFM_DRAM_CTL04_DLL_BYPASS_MODE(v)   BM_DRAM_CTL04_DLL_BYPASS_MODE
#define BF_DRAM_CTL04_DLL_BYPASS_MODE_V(e)  BF_DRAM_CTL04_DLL_BYPASS_MODE(BV_DRAM_CTL04_DLL_BYPASS_MODE__##e)
#define BFM_DRAM_CTL04_DLL_BYPASS_MODE_V(v) BM_DRAM_CTL04_DLL_BYPASS_MODE
#define BP_DRAM_CTL04_DLLLOCKREG            16
#define BM_DRAM_CTL04_DLLLOCKREG            0x10000
#define BF_DRAM_CTL04_DLLLOCKREG(v)         (((v) & 0x1) << 16)
#define BFM_DRAM_CTL04_DLLLOCKREG(v)        BM_DRAM_CTL04_DLLLOCKREG
#define BF_DRAM_CTL04_DLLLOCKREG_V(e)       BF_DRAM_CTL04_DLLLOCKREG(BV_DRAM_CTL04_DLLLOCKREG__##e)
#define BFM_DRAM_CTL04_DLLLOCKREG_V(v)      BM_DRAM_CTL04_DLLLOCKREG
#define BP_DRAM_CTL04_CONCURRENTAP          8
#define BM_DRAM_CTL04_CONCURRENTAP          0x100
#define BF_DRAM_CTL04_CONCURRENTAP(v)       (((v) & 0x1) << 8)
#define BFM_DRAM_CTL04_CONCURRENTAP(v)      BM_DRAM_CTL04_CONCURRENTAP
#define BF_DRAM_CTL04_CONCURRENTAP_V(e)     BF_DRAM_CTL04_CONCURRENTAP(BV_DRAM_CTL04_CONCURRENTAP__##e)
#define BFM_DRAM_CTL04_CONCURRENTAP_V(v)    BM_DRAM_CTL04_CONCURRENTAP
#define BP_DRAM_CTL04_BANK_SPLIT_EN         0
#define BM_DRAM_CTL04_BANK_SPLIT_EN         0x1
#define BF_DRAM_CTL04_BANK_SPLIT_EN(v)      (((v) & 0x1) << 0)
#define BFM_DRAM_CTL04_BANK_SPLIT_EN(v)     BM_DRAM_CTL04_BANK_SPLIT_EN
#define BF_DRAM_CTL04_BANK_SPLIT_EN_V(e)    BF_DRAM_CTL04_BANK_SPLIT_EN(BV_DRAM_CTL04_BANK_SPLIT_EN__##e)
#define BFM_DRAM_CTL04_BANK_SPLIT_EN_V(v)   BM_DRAM_CTL04_BANK_SPLIT_EN

#define HW_DRAM_CTL05                           HW(DRAM_CTL05)
#define HWA_DRAM_CTL05                          (0x800e0000 + 0x14)
#define HWT_DRAM_CTL05                          HWIO_32_RW
#define HWN_DRAM_CTL05                          DRAM_CTL05
#define HWI_DRAM_CTL05                          
#define BP_DRAM_CTL05_INTRPTREADA               24
#define BM_DRAM_CTL05_INTRPTREADA               0x1000000
#define BF_DRAM_CTL05_INTRPTREADA(v)            (((v) & 0x1) << 24)
#define BFM_DRAM_CTL05_INTRPTREADA(v)           BM_DRAM_CTL05_INTRPTREADA
#define BF_DRAM_CTL05_INTRPTREADA_V(e)          BF_DRAM_CTL05_INTRPTREADA(BV_DRAM_CTL05_INTRPTREADA__##e)
#define BFM_DRAM_CTL05_INTRPTREADA_V(v)         BM_DRAM_CTL05_INTRPTREADA
#define BP_DRAM_CTL05_INTRPTAPBURST             16
#define BM_DRAM_CTL05_INTRPTAPBURST             0x10000
#define BF_DRAM_CTL05_INTRPTAPBURST(v)          (((v) & 0x1) << 16)
#define BFM_DRAM_CTL05_INTRPTAPBURST(v)         BM_DRAM_CTL05_INTRPTAPBURST
#define BF_DRAM_CTL05_INTRPTAPBURST_V(e)        BF_DRAM_CTL05_INTRPTAPBURST(BV_DRAM_CTL05_INTRPTAPBURST__##e)
#define BFM_DRAM_CTL05_INTRPTAPBURST_V(v)       BM_DRAM_CTL05_INTRPTAPBURST
#define BP_DRAM_CTL05_FAST_WRITE                8
#define BM_DRAM_CTL05_FAST_WRITE                0x100
#define BF_DRAM_CTL05_FAST_WRITE(v)             (((v) & 0x1) << 8)
#define BFM_DRAM_CTL05_FAST_WRITE(v)            BM_DRAM_CTL05_FAST_WRITE
#define BF_DRAM_CTL05_FAST_WRITE_V(e)           BF_DRAM_CTL05_FAST_WRITE(BV_DRAM_CTL05_FAST_WRITE__##e)
#define BFM_DRAM_CTL05_FAST_WRITE_V(v)          BM_DRAM_CTL05_FAST_WRITE
#define BP_DRAM_CTL05_EN_LOWPOWER_MODE          0
#define BM_DRAM_CTL05_EN_LOWPOWER_MODE          0x1
#define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v)       (((v) & 0x1) << 0)
#define BFM_DRAM_CTL05_EN_LOWPOWER_MODE(v)      BM_DRAM_CTL05_EN_LOWPOWER_MODE
#define BF_DRAM_CTL05_EN_LOWPOWER_MODE_V(e)     BF_DRAM_CTL05_EN_LOWPOWER_MODE(BV_DRAM_CTL05_EN_LOWPOWER_MODE__##e)
#define BFM_DRAM_CTL05_EN_LOWPOWER_MODE_V(v)    BM_DRAM_CTL05_EN_LOWPOWER_MODE

#define HW_DRAM_CTL06                       HW(DRAM_CTL06)
#define HWA_DRAM_CTL06                      (0x800e0000 + 0x18)
#define HWT_DRAM_CTL06                      HWIO_32_RW
#define HWN_DRAM_CTL06                      DRAM_CTL06
#define HWI_DRAM_CTL06                      
#define BP_DRAM_CTL06_POWER_DOWN            24
#define BM_DRAM_CTL06_POWER_DOWN            0x1000000
#define BF_DRAM_CTL06_POWER_DOWN(v)         (((v) & 0x1) << 24)
#define BFM_DRAM_CTL06_POWER_DOWN(v)        BM_DRAM_CTL06_POWER_DOWN
#define BF_DRAM_CTL06_POWER_DOWN_V(e)       BF_DRAM_CTL06_POWER_DOWN(BV_DRAM_CTL06_POWER_DOWN__##e)
#define BFM_DRAM_CTL06_POWER_DOWN_V(v)      BM_DRAM_CTL06_POWER_DOWN
#define BP_DRAM_CTL06_PLACEMENT_EN          16
#define BM_DRAM_CTL06_PLACEMENT_EN          0x10000
#define BF_DRAM_CTL06_PLACEMENT_EN(v)       (((v) & 0x1) << 16)
#define BFM_DRAM_CTL06_PLACEMENT_EN(v)      BM_DRAM_CTL06_PLACEMENT_EN
#define BF_DRAM_CTL06_PLACEMENT_EN_V(e)     BF_DRAM_CTL06_PLACEMENT_EN(BV_DRAM_CTL06_PLACEMENT_EN__##e)
#define BFM_DRAM_CTL06_PLACEMENT_EN_V(v)    BM_DRAM_CTL06_PLACEMENT_EN
#define BP_DRAM_CTL06_NO_CMD_INIT           8
#define BM_DRAM_CTL06_NO_CMD_INIT           0x100
#define BF_DRAM_CTL06_NO_CMD_INIT(v)        (((v) & 0x1) << 8)
#define BFM_DRAM_CTL06_NO_CMD_INIT(v)       BM_DRAM_CTL06_NO_CMD_INIT
#define BF_DRAM_CTL06_NO_CMD_INIT_V(e)      BF_DRAM_CTL06_NO_CMD_INIT(BV_DRAM_CTL06_NO_CMD_INIT__##e)
#define BFM_DRAM_CTL06_NO_CMD_INIT_V(v)     BM_DRAM_CTL06_NO_CMD_INIT
#define BP_DRAM_CTL06_INTRPTWRITEA          0
#define BM_DRAM_CTL06_INTRPTWRITEA          0x1
#define BF_DRAM_CTL06_INTRPTWRITEA(v)       (((v) & 0x1) << 0)
#define BFM_DRAM_CTL06_INTRPTWRITEA(v)      BM_DRAM_CTL06_INTRPTWRITEA
#define BF_DRAM_CTL06_INTRPTWRITEA_V(e)     BF_DRAM_CTL06_INTRPTWRITEA(BV_DRAM_CTL06_INTRPTWRITEA__##e)
#define BFM_DRAM_CTL06_INTRPTWRITEA_V(v)    BM_DRAM_CTL06_INTRPTWRITEA

#define HW_DRAM_CTL07                       HW(DRAM_CTL07)
#define HWA_DRAM_CTL07                      (0x800e0000 + 0x1c)
#define HWT_DRAM_CTL07                      HWIO_32_RW
#define HWN_DRAM_CTL07                      DRAM_CTL07
#define HWI_DRAM_CTL07                      
#define BP_DRAM_CTL07_RW_SAME_EN            24
#define BM_DRAM_CTL07_RW_SAME_EN            0x1000000
#define BF_DRAM_CTL07_RW_SAME_EN(v)         (((v) & 0x1) << 24)
#define BFM_DRAM_CTL07_RW_SAME_EN(v)        BM_DRAM_CTL07_RW_SAME_EN
#define BF_DRAM_CTL07_RW_SAME_EN_V(e)       BF_DRAM_CTL07_RW_SAME_EN(BV_DRAM_CTL07_RW_SAME_EN__##e)
#define BFM_DRAM_CTL07_RW_SAME_EN_V(v)      BM_DRAM_CTL07_RW_SAME_EN
#define BP_DRAM_CTL07_REG_DIMM_ENABLE       16
#define BM_DRAM_CTL07_REG_DIMM_ENABLE       0x10000
#define BF_DRAM_CTL07_REG_DIMM_ENABLE(v)    (((v) & 0x1) << 16)
#define BFM_DRAM_CTL07_REG_DIMM_ENABLE(v)   BM_DRAM_CTL07_REG_DIMM_ENABLE
#define BF_DRAM_CTL07_REG_DIMM_ENABLE_V(e)  BF_DRAM_CTL07_REG_DIMM_ENABLE(BV_DRAM_CTL07_REG_DIMM_ENABLE__##e)
#define BFM_DRAM_CTL07_REG_DIMM_ENABLE_V(v) BM_DRAM_CTL07_REG_DIMM_ENABLE
#define BP_DRAM_CTL07_RD2RD_TURN            8
#define BM_DRAM_CTL07_RD2RD_TURN            0x100
#define BF_DRAM_CTL07_RD2RD_TURN(v)         (((v) & 0x1) << 8)
#define BFM_DRAM_CTL07_RD2RD_TURN(v)        BM_DRAM_CTL07_RD2RD_TURN
#define BF_DRAM_CTL07_RD2RD_TURN_V(e)       BF_DRAM_CTL07_RD2RD_TURN(BV_DRAM_CTL07_RD2RD_TURN__##e)
#define BFM_DRAM_CTL07_RD2RD_TURN_V(v)      BM_DRAM_CTL07_RD2RD_TURN
#define BP_DRAM_CTL07_PRIORITY_EN           0
#define BM_DRAM_CTL07_PRIORITY_EN           0x1
#define BF_DRAM_CTL07_PRIORITY_EN(v)        (((v) & 0x1) << 0)
#define BFM_DRAM_CTL07_PRIORITY_EN(v)       BM_DRAM_CTL07_PRIORITY_EN
#define BF_DRAM_CTL07_PRIORITY_EN_V(e)      BF_DRAM_CTL07_PRIORITY_EN(BV_DRAM_CTL07_PRIORITY_EN__##e)
#define BFM_DRAM_CTL07_PRIORITY_EN_V(v)     BM_DRAM_CTL07_PRIORITY_EN

#define HW_DRAM_CTL08                       HW(DRAM_CTL08)
#define HWA_DRAM_CTL08                      (0x800e0000 + 0x20)
#define HWT_DRAM_CTL08                      HWIO_32_RW
#define HWN_DRAM_CTL08                      DRAM_CTL08
#define HWI_DRAM_CTL08                      
#define BP_DRAM_CTL08_TRAS_LOCKOUT          24
#define BM_DRAM_CTL08_TRAS_LOCKOUT          0x1000000
#define BF_DRAM_CTL08_TRAS_LOCKOUT(v)       (((v) & 0x1) << 24)
#define BFM_DRAM_CTL08_TRAS_LOCKOUT(v)      BM_DRAM_CTL08_TRAS_LOCKOUT
#define BF_DRAM_CTL08_TRAS_LOCKOUT_V(e)     BF_DRAM_CTL08_TRAS_LOCKOUT(BV_DRAM_CTL08_TRAS_LOCKOUT__##e)
#define BFM_DRAM_CTL08_TRAS_LOCKOUT_V(v)    BM_DRAM_CTL08_TRAS_LOCKOUT
#define BP_DRAM_CTL08_START                 16
#define BM_DRAM_CTL08_START                 0x10000
#define BF_DRAM_CTL08_START(v)              (((v) & 0x1) << 16)
#define BFM_DRAM_CTL08_START(v)             BM_DRAM_CTL08_START
#define BF_DRAM_CTL08_START_V(e)            BF_DRAM_CTL08_START(BV_DRAM_CTL08_START__##e)
#define BFM_DRAM_CTL08_START_V(v)           BM_DRAM_CTL08_START
#define BP_DRAM_CTL08_SREFRESH              8
#define BM_DRAM_CTL08_SREFRESH              0x100
#define BF_DRAM_CTL08_SREFRESH(v)           (((v) & 0x1) << 8)
#define BFM_DRAM_CTL08_SREFRESH(v)          BM_DRAM_CTL08_SREFRESH
#define BF_DRAM_CTL08_SREFRESH_V(e)         BF_DRAM_CTL08_SREFRESH(BV_DRAM_CTL08_SREFRESH__##e)
#define BFM_DRAM_CTL08_SREFRESH_V(v)        BM_DRAM_CTL08_SREFRESH
#define BP_DRAM_CTL08_SDR_MODE              0
#define BM_DRAM_CTL08_SDR_MODE              0x1
#define BF_DRAM_CTL08_SDR_MODE(v)           (((v) & 0x1) << 0)
#define BFM_DRAM_CTL08_SDR_MODE(v)          BM_DRAM_CTL08_SDR_MODE
#define BF_DRAM_CTL08_SDR_MODE_V(e)         BF_DRAM_CTL08_SDR_MODE(BV_DRAM_CTL08_SDR_MODE__##e)
#define BFM_DRAM_CTL08_SDR_MODE_V(v)        BM_DRAM_CTL08_SDR_MODE

#define HW_DRAM_CTL09                               HW(DRAM_CTL09)
#define HWA_DRAM_CTL09                              (0x800e0000 + 0x24)
#define HWT_DRAM_CTL09                              HWIO_32_RW
#define HWN_DRAM_CTL09                              DRAM_CTL09
#define HWI_DRAM_CTL09                              
#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE             24
#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE             0x3000000
#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v)          (((v) & 0x3) << 24)
#define BFM_DRAM_CTL09_OUT_OF_RANGE_TYPE(v)         BM_DRAM_CTL09_OUT_OF_RANGE_TYPE
#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE_V(e)        BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(BV_DRAM_CTL09_OUT_OF_RANGE_TYPE__##e)
#define BFM_DRAM_CTL09_OUT_OF_RANGE_TYPE_V(v)       BM_DRAM_CTL09_OUT_OF_RANGE_TYPE
#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID        16
#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID        0x30000
#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v)     (((v) & 0x3) << 16)
#define BFM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v)    BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID
#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID_V(e)   BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(BV_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID__##e)
#define BFM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID_V(v)  BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID
#define BP_DRAM_CTL09_WRITE_MODEREG                 8
#define BM_DRAM_CTL09_WRITE_MODEREG                 0x100
#define BF_DRAM_CTL09_WRITE_MODEREG(v)              (((v) & 0x1) << 8)
#define BFM_DRAM_CTL09_WRITE_MODEREG(v)             BM_DRAM_CTL09_WRITE_MODEREG
#define BF_DRAM_CTL09_WRITE_MODEREG_V(e)            BF_DRAM_CTL09_WRITE_MODEREG(BV_DRAM_CTL09_WRITE_MODEREG__##e)
#define BFM_DRAM_CTL09_WRITE_MODEREG_V(v)           BM_DRAM_CTL09_WRITE_MODEREG
#define BP_DRAM_CTL09_WRITEINTERP                   0
#define BM_DRAM_CTL09_WRITEINTERP                   0x1
#define BF_DRAM_CTL09_WRITEINTERP(v)                (((v) & 0x1) << 0)
#define BFM_DRAM_CTL09_WRITEINTERP(v)               BM_DRAM_CTL09_WRITEINTERP
#define BF_DRAM_CTL09_WRITEINTERP_V(e)              BF_DRAM_CTL09_WRITEINTERP(BV_DRAM_CTL09_WRITEINTERP__##e)
#define BFM_DRAM_CTL09_WRITEINTERP_V(v)             BM_DRAM_CTL09_WRITEINTERP

#define HW_DRAM_CTL10                   HW(DRAM_CTL10)
#define HWA_DRAM_CTL10                  (0x800e0000 + 0x28)
#define HWT_DRAM_CTL10                  HWIO_32_RW
#define HWN_DRAM_CTL10                  DRAM_CTL10
#define HWI_DRAM_CTL10                  
#define BP_DRAM_CTL10_AGE_COUNT         24
#define BM_DRAM_CTL10_AGE_COUNT         0x7000000
#define BF_DRAM_CTL10_AGE_COUNT(v)      (((v) & 0x7) << 24)
#define BFM_DRAM_CTL10_AGE_COUNT(v)     BM_DRAM_CTL10_AGE_COUNT
#define BF_DRAM_CTL10_AGE_COUNT_V(e)    BF_DRAM_CTL10_AGE_COUNT(BV_DRAM_CTL10_AGE_COUNT__##e)
#define BFM_DRAM_CTL10_AGE_COUNT_V(v)   BM_DRAM_CTL10_AGE_COUNT
#define BP_DRAM_CTL10_ADDR_PINS         16
#define BM_DRAM_CTL10_ADDR_PINS         0x70000
#define BF_DRAM_CTL10_ADDR_PINS(v)      (((v) & 0x7) << 16)
#define BFM_DRAM_CTL10_ADDR_PINS(v)     BM_DRAM_CTL10_ADDR_PINS
#define BF_DRAM_CTL10_ADDR_PINS_V(e)    BF_DRAM_CTL10_ADDR_PINS(BV_DRAM_CTL10_ADDR_PINS__##e)
#define BFM_DRAM_CTL10_ADDR_PINS_V(v)   BM_DRAM_CTL10_ADDR_PINS
#define BP_DRAM_CTL10_TEMRS             8
#define BM_DRAM_CTL10_TEMRS             0x300
#define BF_DRAM_CTL10_TEMRS(v)          (((v) & 0x3) << 8)
#define BFM_DRAM_CTL10_TEMRS(v)         BM_DRAM_CTL10_TEMRS
#define BF_DRAM_CTL10_TEMRS_V(e)        BF_DRAM_CTL10_TEMRS(BV_DRAM_CTL10_TEMRS__##e)
#define BFM_DRAM_CTL10_TEMRS_V(v)       BM_DRAM_CTL10_TEMRS
#define BP_DRAM_CTL10_Q_FULLNESS        0
#define BM_DRAM_CTL10_Q_FULLNESS        0x3
#define BF_DRAM_CTL10_Q_FULLNESS(v)     (((v) & 0x3) << 0)
#define BFM_DRAM_CTL10_Q_FULLNESS(v)    BM_DRAM_CTL10_Q_FULLNESS
#define BF_DRAM_CTL10_Q_FULLNESS_V(e)   BF_DRAM_CTL10_Q_FULLNESS(BV_DRAM_CTL10_Q_FULLNESS__##e)
#define BFM_DRAM_CTL10_Q_FULLNESS_V(v)  BM_DRAM_CTL10_Q_FULLNESS

#define HW_DRAM_CTL11                           HW(DRAM_CTL11)
#define HWA_DRAM_CTL11                          (0x800e0000 + 0x2c)
#define HWT_DRAM_CTL11                          HWIO_32_RW
#define HWN_DRAM_CTL11                          DRAM_CTL11
#define HWI_DRAM_CTL11                          
#define BP_DRAM_CTL11_MAX_CS_REG                24
#define BM_DRAM_CTL11_MAX_CS_REG                0x7000000
#define BF_DRAM_CTL11_MAX_CS_REG(v)             (((v) & 0x7) << 24)
#define BFM_DRAM_CTL11_MAX_CS_REG(v)            BM_DRAM_CTL11_MAX_CS_REG
#define BF_DRAM_CTL11_MAX_CS_REG_V(e)           BF_DRAM_CTL11_MAX_CS_REG(BV_DRAM_CTL11_MAX_CS_REG__##e)
#define BFM_DRAM_CTL11_MAX_CS_REG_V(v)          BM_DRAM_CTL11_MAX_CS_REG
#define BP_DRAM_CTL11_COMMAND_AGE_COUNT         16
#define BM_DRAM_CTL11_COMMAND_AGE_COUNT         0x70000
#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v)      (((v) & 0x7) << 16)
#define BFM_DRAM_CTL11_COMMAND_AGE_COUNT(v)     BM_DRAM_CTL11_COMMAND_AGE_COUNT
#define BF_DRAM_CTL11_COMMAND_AGE_COUNT_V(e)    BF_DRAM_CTL11_COMMAND_AGE_COUNT(BV_DRAM_CTL11_COMMAND_AGE_COUNT__##e)
#define BFM_DRAM_CTL11_COMMAND_AGE_COUNT_V(v)   BM_DRAM_CTL11_COMMAND_AGE_COUNT
#define BP_DRAM_CTL11_COLUMN_SIZE               8
#define BM_DRAM_CTL11_COLUMN_SIZE               0x700
#define BF_DRAM_CTL11_COLUMN_SIZE(v)            (((v) & 0x7) << 8)
#define BFM_DRAM_CTL11_COLUMN_SIZE(v)           BM_DRAM_CTL11_COLUMN_SIZE
#define BF_DRAM_CTL11_COLUMN_SIZE_V(e)          BF_DRAM_CTL11_COLUMN_SIZE(BV_DRAM_CTL11_COLUMN_SIZE__##e)
#define BFM_DRAM_CTL11_COLUMN_SIZE_V(v)         BM_DRAM_CTL11_COLUMN_SIZE
#define BP_DRAM_CTL11_CASLAT                    0
#define BM_DRAM_CTL11_CASLAT                    0x7
#define BF_DRAM_CTL11_CASLAT(v)                 (((v) & 0x7) << 0)
#define BFM_DRAM_CTL11_CASLAT(v)                BM_DRAM_CTL11_CASLAT
#define BF_DRAM_CTL11_CASLAT_V(e)               BF_DRAM_CTL11_CASLAT(BV_DRAM_CTL11_CASLAT__##e)
#define BFM_DRAM_CTL11_CASLAT_V(v)              BM_DRAM_CTL11_CASLAT

#define HW_DRAM_CTL12               HW(DRAM_CTL12)
#define HWA_DRAM_CTL12              (0x800e0000 + 0x30)
#define HWT_DRAM_CTL12              HWIO_32_RW
#define HWN_DRAM_CTL12              DRAM_CTL12
#define HWI_DRAM_CTL12              
#define BP_DRAM_CTL12_TWR_INT       24
#define BM_DRAM_CTL12_TWR_INT       0x7000000
#define BF_DRAM_CTL12_TWR_INT(v)    (((v) & 0x7) << 24)
#define BFM_DRAM_CTL12_TWR_INT(v)   BM_DRAM_CTL12_TWR_INT
#define BF_DRAM_CTL12_TWR_INT_V(e)  BF_DRAM_CTL12_TWR_INT(BV_DRAM_CTL12_TWR_INT__##e)
#define BFM_DRAM_CTL12_TWR_INT_V(v) BM_DRAM_CTL12_TWR_INT
#define BP_DRAM_CTL12_TRRD          16
#define BM_DRAM_CTL12_TRRD          0x70000
#define BF_DRAM_CTL12_TRRD(v)       (((v) & 0x7) << 16)
#define BFM_DRAM_CTL12_TRRD(v)      BM_DRAM_CTL12_TRRD
#define BF_DRAM_CTL12_TRRD_V(e)     BF_DRAM_CTL12_TRRD(BV_DRAM_CTL12_TRRD__##e)
#define BFM_DRAM_CTL12_TRRD_V(v)    BM_DRAM_CTL12_TRRD
#define BP_DRAM_CTL12_TCKE          0
#define BM_DRAM_CTL12_TCKE          0x7
#define BF_DRAM_CTL12_TCKE(v)       (((v) & 0x7) << 0)
#define BFM_DRAM_CTL12_TCKE(v)      BM_DRAM_CTL12_TCKE
#define BF_DRAM_CTL12_TCKE_V(e)     BF_DRAM_CTL12_TCKE(BV_DRAM_CTL12_TCKE__##e)
#define BFM_DRAM_CTL12_TCKE_V(v)    BM_DRAM_CTL12_TCKE

#define HW_DRAM_CTL13                       HW(DRAM_CTL13)
#define HWA_DRAM_CTL13                      (0x800e0000 + 0x34)
#define HWT_DRAM_CTL13                      HWIO_32_RW
#define HWN_DRAM_CTL13                      DRAM_CTL13
#define HWI_DRAM_CTL13                      
#define BP_DRAM_CTL13_CASLAT_LIN_GATE       24
#define BM_DRAM_CTL13_CASLAT_LIN_GATE       0xf000000
#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v)    (((v) & 0xf) << 24)
#define BFM_DRAM_CTL13_CASLAT_LIN_GATE(v)   BM_DRAM_CTL13_CASLAT_LIN_GATE
#define BF_DRAM_CTL13_CASLAT_LIN_GATE_V(e)  BF_DRAM_CTL13_CASLAT_LIN_GATE(BV_DRAM_CTL13_CASLAT_LIN_GATE__##e)
#define BFM_DRAM_CTL13_CASLAT_LIN_GATE_V(v) BM_DRAM_CTL13_CASLAT_LIN_GATE
#define BP_DRAM_CTL13_CASLAT_LIN            16
#define BM_DRAM_CTL13_CASLAT_LIN            0xf0000
#define BF_DRAM_CTL13_CASLAT_LIN(v)         (((v) & 0xf) << 16)
#define BFM_DRAM_CTL13_CASLAT_LIN(v)        BM_DRAM_CTL13_CASLAT_LIN
#define BF_DRAM_CTL13_CASLAT_LIN_V(e)       BF_DRAM_CTL13_CASLAT_LIN(BV_DRAM_CTL13_CASLAT_LIN__##e)
#define BFM_DRAM_CTL13_CASLAT_LIN_V(v)      BM_DRAM_CTL13_CASLAT_LIN
#define BP_DRAM_CTL13_APREBIT               8
#define BM_DRAM_CTL13_APREBIT               0xf00
#define BF_DRAM_CTL13_APREBIT(v)            (((v) & 0xf) << 8)
#define BFM_DRAM_CTL13_APREBIT(v)           BM_DRAM_CTL13_APREBIT
#define BF_DRAM_CTL13_APREBIT_V(e)          BF_DRAM_CTL13_APREBIT(BV_DRAM_CTL13_APREBIT__##e)
#define BFM_DRAM_CTL13_APREBIT_V(v)         BM_DRAM_CTL13_APREBIT
#define BP_DRAM_CTL13_TWTR                  0
#define BM_DRAM_CTL13_TWTR                  0x7
#define BF_DRAM_CTL13_TWTR(v)               (((v) & 0x7) << 0)
#define BFM_DRAM_CTL13_TWTR(v)              BM_DRAM_CTL13_TWTR
#define BF_DRAM_CTL13_TWTR_V(e)             BF_DRAM_CTL13_TWTR(BV_DRAM_CTL13_TWTR__##e)
#define BFM_DRAM_CTL13_TWTR_V(v)            BM_DRAM_CTL13_TWTR

#define HW_DRAM_CTL14                               HW(DRAM_CTL14)
#define HWA_DRAM_CTL14                              (0x800e0000 + 0x38)
#define HWT_DRAM_CTL14                              HWIO_32_RW
#define HWN_DRAM_CTL14                              DRAM_CTL14
#define HWI_DRAM_CTL14                              
#define BP_DRAM_CTL14_MAX_COL_REG                   24
#define BM_DRAM_CTL14_MAX_COL_REG                   0xf000000
#define BF_DRAM_CTL14_MAX_COL_REG(v)                (((v) & 0xf) << 24)
#define BFM_DRAM_CTL14_MAX_COL_REG(v)               BM_DRAM_CTL14_MAX_COL_REG
#define BF_DRAM_CTL14_MAX_COL_REG_V(e)              BF_DRAM_CTL14_MAX_COL_REG(BV_DRAM_CTL14_MAX_COL_REG__##e)
#define BFM_DRAM_CTL14_MAX_COL_REG_V(v)             BM_DRAM_CTL14_MAX_COL_REG
#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       16
#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       0xf0000
#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v)    (((v) & 0xf) << 16)
#define BFM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v)   BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE
#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE_V(e)  BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(BV_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE__##e)
#define BFM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE_V(v) BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE
#define BP_DRAM_CTL14_INITAREF                      8
#define BM_DRAM_CTL14_INITAREF                      0xf00
#define BF_DRAM_CTL14_INITAREF(v)                   (((v) & 0xf) << 8)
#define BFM_DRAM_CTL14_INITAREF(v)                  BM_DRAM_CTL14_INITAREF
#define BF_DRAM_CTL14_INITAREF_V(e)                 BF_DRAM_CTL14_INITAREF(BV_DRAM_CTL14_INITAREF__##e)
#define BFM_DRAM_CTL14_INITAREF_V(v)                BM_DRAM_CTL14_INITAREF
#define BP_DRAM_CTL14_CS_MAP                        0
#define BM_DRAM_CTL14_CS_MAP                        0xf
#define BF_DRAM_CTL14_CS_MAP(v)                     (((v) & 0xf) << 0)
#define BFM_DRAM_CTL14_CS_MAP(v)                    BM_DRAM_CTL14_CS_MAP
#define BF_DRAM_CTL14_CS_MAP_V(e)                   BF_DRAM_CTL14_CS_MAP(BV_DRAM_CTL14_CS_MAP__##e)
#define BFM_DRAM_CTL14_CS_MAP_V(v)                  BM_DRAM_CTL14_CS_MAP

#define HW_DRAM_CTL15                   HW(DRAM_CTL15)
#define HWA_DRAM_CTL15                  (0x800e0000 + 0x3c)
#define HWT_DRAM_CTL15                  HWIO_32_RW
#define HWN_DRAM_CTL15                  DRAM_CTL15
#define HWI_DRAM_CTL15                  
#define BP_DRAM_CTL15_TRP               24
#define BM_DRAM_CTL15_TRP               0xf000000
#define BF_DRAM_CTL15_TRP(v)            (((v) & 0xf) << 24)
#define BFM_DRAM_CTL15_TRP(v)           BM_DRAM_CTL15_TRP
#define BF_DRAM_CTL15_TRP_V(e)          BF_DRAM_CTL15_TRP(BV_DRAM_CTL15_TRP__##e)
#define BFM_DRAM_CTL15_TRP_V(v)         BM_DRAM_CTL15_TRP
#define BP_DRAM_CTL15_TDAL              16
#define BM_DRAM_CTL15_TDAL              0xf0000
#define BF_DRAM_CTL15_TDAL(v)           (((v) & 0xf) << 16)
#define BFM_DRAM_CTL15_TDAL(v)          BM_DRAM_CTL15_TDAL
#define BF_DRAM_CTL15_TDAL_V(e)         BF_DRAM_CTL15_TDAL(BV_DRAM_CTL15_TDAL__##e)
#define BFM_DRAM_CTL15_TDAL_V(v)        BM_DRAM_CTL15_TDAL
#define BP_DRAM_CTL15_PORT_BUSY         8
#define BM_DRAM_CTL15_PORT_BUSY         0xf00
#define BF_DRAM_CTL15_PORT_BUSY(v)      (((v) & 0xf) << 8)
#define BFM_DRAM_CTL15_PORT_BUSY(v)     BM_DRAM_CTL15_PORT_BUSY
#define BF_DRAM_CTL15_PORT_BUSY_V(e)    BF_DRAM_CTL15_PORT_BUSY(BV_DRAM_CTL15_PORT_BUSY__##e)
#define BFM_DRAM_CTL15_PORT_BUSY_V(v)   BM_DRAM_CTL15_PORT_BUSY
#define BP_DRAM_CTL15_MAX_ROW_REG       0
#define BM_DRAM_CTL15_MAX_ROW_REG       0xf
#define BF_DRAM_CTL15_MAX_ROW_REG(v)    (((v) & 0xf) << 0)
#define BFM_DRAM_CTL15_MAX_ROW_REG(v)   BM_DRAM_CTL15_MAX_ROW_REG
#define BF_DRAM_CTL15_MAX_ROW_REG_V(e)  BF_DRAM_CTL15_MAX_ROW_REG(BV_DRAM_CTL15_MAX_ROW_REG__##e)
#define BFM_DRAM_CTL15_MAX_ROW_REG_V(v) BM_DRAM_CTL15_MAX_ROW_REG

#define HW_DRAM_CTL16                               HW(DRAM_CTL16)
#define HWA_DRAM_CTL16                              (0x800e0000 + 0x40)
#define HWT_DRAM_CTL16                              HWIO_32_RW
#define HWN_DRAM_CTL16                              DRAM_CTL16
#define HWI_DRAM_CTL16                              
#define BP_DRAM_CTL16_TMRD                          24
#define BM_DRAM_CTL16_TMRD                          0x1f000000
#define BF_DRAM_CTL16_TMRD(v)                       (((v) & 0x1f) << 24)
#define BFM_DRAM_CTL16_TMRD(v)                      BM_DRAM_CTL16_TMRD
#define BF_DRAM_CTL16_TMRD_V(e)                     BF_DRAM_CTL16_TMRD(BV_DRAM_CTL16_TMRD__##e)
#define BFM_DRAM_CTL16_TMRD_V(v)                    BM_DRAM_CTL16_TMRD
#define BP_DRAM_CTL16_LOWPOWER_CONTROL              16
#define BM_DRAM_CTL16_LOWPOWER_CONTROL              0x1f0000
#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v)           (((v) & 0x1f) << 16)
#define BFM_DRAM_CTL16_LOWPOWER_CONTROL(v)          BM_DRAM_CTL16_LOWPOWER_CONTROL
#define BF_DRAM_CTL16_LOWPOWER_CONTROL_V(e)         BF_DRAM_CTL16_LOWPOWER_CONTROL(BV_DRAM_CTL16_LOWPOWER_CONTROL__##e)
#define BFM_DRAM_CTL16_LOWPOWER_CONTROL_V(v)        BM_DRAM_CTL16_LOWPOWER_CONTROL
#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE          8
#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE          0x1f00
#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v)       (((v) & 0x1f) << 8)
#define BFM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v)      BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE
#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE_V(e)     BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(BV_DRAM_CTL16_LOWPOWER_AUTO_ENABLE__##e)
#define BFM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE_V(v)    BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE
#define BP_DRAM_CTL16_INT_ACK                       0
#define BM_DRAM_CTL16_INT_ACK                       0xf
#define BF_DRAM_CTL16_INT_ACK(v)                    (((v) & 0xf) << 0)
#define BFM_DRAM_CTL16_INT_ACK(v)                   BM_DRAM_CTL16_INT_ACK
#define BF_DRAM_CTL16_INT_ACK_V(e)                  BF_DRAM_CTL16_INT_ACK(BV_DRAM_CTL16_INT_ACK__##e)
#define BFM_DRAM_CTL16_INT_ACK_V(v)                 BM_DRAM_CTL16_INT_ACK

#define HW_DRAM_CTL17                       HW(DRAM_CTL17)
#define HWA_DRAM_CTL17                      (0x800e0000 + 0x44)
#define HWT_DRAM_CTL17                      HWIO_32_RW
#define HWN_DRAM_CTL17                      DRAM_CTL17
#define HWI_DRAM_CTL17                      
#define BP_DRAM_CTL17_DLL_START_POINT       24
#define BM_DRAM_CTL17_DLL_START_POINT       0xff000000
#define BF_DRAM_CTL17_DLL_START_POINT(v)    (((v) & 0xff) << 24)
#define BFM_DRAM_CTL17_DLL_START_POINT(v)   BM_DRAM_CTL17_DLL_START_POINT
#define BF_DRAM_CTL17_DLL_START_POINT_V(e)  BF_DRAM_CTL17_DLL_START_POINT(BV_DRAM_CTL17_DLL_START_POINT__##e)
#define BFM_DRAM_CTL17_DLL_START_POINT_V(v) BM_DRAM_CTL17_DLL_START_POINT
#define BP_DRAM_CTL17_DLL_LOCK              16
#define BM_DRAM_CTL17_DLL_LOCK              0xff0000
#define BF_DRAM_CTL17_DLL_LOCK(v)           (((v) & 0xff) << 16)
#define BFM_DRAM_CTL17_DLL_LOCK(v)          BM_DRAM_CTL17_DLL_LOCK
#define BF_DRAM_CTL17_DLL_LOCK_V(e)         BF_DRAM_CTL17_DLL_LOCK(BV_DRAM_CTL17_DLL_LOCK__##e)
#define BFM_DRAM_CTL17_DLL_LOCK_V(v)        BM_DRAM_CTL17_DLL_LOCK
#define BP_DRAM_CTL17_DLL_INCREMENT         8
#define BM_DRAM_CTL17_DLL_INCREMENT         0xff00
#define BF_DRAM_CTL17_DLL_INCREMENT(v)      (((v) & 0xff) << 8)
#define BFM_DRAM_CTL17_DLL_INCREMENT(v)     BM_DRAM_CTL17_DLL_INCREMENT
#define BF_DRAM_CTL17_DLL_INCREMENT_V(e)    BF_DRAM_CTL17_DLL_INCREMENT(BV_DRAM_CTL17_DLL_INCREMENT__##e)
#define BFM_DRAM_CTL17_DLL_INCREMENT_V(v)   BM_DRAM_CTL17_DLL_INCREMENT
#define BP_DRAM_CTL17_TRC                   0
#define BM_DRAM_CTL17_TRC                   0x1f
#define BF_DRAM_CTL17_TRC(v)                (((v) & 0x1f) << 0)
#define BFM_DRAM_CTL17_TRC(v)               BM_DRAM_CTL17_TRC
#define BF_DRAM_CTL17_TRC_V(e)              BF_DRAM_CTL17_TRC(BV_DRAM_CTL17_TRC__##e)
#define BFM_DRAM_CTL17_TRC_V(v)             BM_DRAM_CTL17_TRC

#define HW_DRAM_CTL18                       HW(DRAM_CTL18)
#define HWA_DRAM_CTL18                      (0x800e0000 + 0x48)
#define HWT_DRAM_CTL18                      HWIO_32_RW
#define HWN_DRAM_CTL18                      DRAM_CTL18
#define HWI_DRAM_CTL18                      
#define BP_DRAM_CTL18_DLL_DQS_DELAY_1       24
#define BM_DRAM_CTL18_DLL_DQS_DELAY_1       0x7f000000
#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v)    (((v) & 0x7f) << 24)
#define BFM_DRAM_CTL18_DLL_DQS_DELAY_1(v)   BM_DRAM_CTL18_DLL_DQS_DELAY_1
#define BF_DRAM_CTL18_DLL_DQS_DELAY_1_V(e)  BF_DRAM_CTL18_DLL_DQS_DELAY_1(BV_DRAM_CTL18_DLL_DQS_DELAY_1__##e)
#define BFM_DRAM_CTL18_DLL_DQS_DELAY_1_V(v) BM_DRAM_CTL18_DLL_DQS_DELAY_1
#define BP_DRAM_CTL18_DLL_DQS_DELAY_0       16
#define BM_DRAM_CTL18_DLL_DQS_DELAY_0       0x7f0000
#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v)    (((v) & 0x7f) << 16)
#define BFM_DRAM_CTL18_DLL_DQS_DELAY_0(v)   BM_DRAM_CTL18_DLL_DQS_DELAY_0
#define BF_DRAM_CTL18_DLL_DQS_DELAY_0_V(e)  BF_DRAM_CTL18_DLL_DQS_DELAY_0(BV_DRAM_CTL18_DLL_DQS_DELAY_0__##e)
#define BFM_DRAM_CTL18_DLL_DQS_DELAY_0_V(v) BM_DRAM_CTL18_DLL_DQS_DELAY_0
#define BP_DRAM_CTL18_INT_STATUS            8
#define BM_DRAM_CTL18_INT_STATUS            0x1f00
#define BF_DRAM_CTL18_INT_STATUS(v)         (((v) & 0x1f) << 8)
#define BFM_DRAM_CTL18_INT_STATUS(v)        BM_DRAM_CTL18_INT_STATUS
#define BF_DRAM_CTL18_INT_STATUS_V(e)       BF_DRAM_CTL18_INT_STATUS(BV_DRAM_CTL18_INT_STATUS__##e)
#define BFM_DRAM_CTL18_INT_STATUS_V(v)      BM_DRAM_CTL18_INT_STATUS
#define BP_DRAM_CTL18_INT_MASK              0
#define BM_DRAM_CTL18_INT_MASK              0x1f
#define BF_DRAM_CTL18_INT_MASK(v)           (((v) & 0x1f) << 0)
#define BFM_DRAM_CTL18_INT_MASK(v)          BM_DRAM_CTL18_INT_MASK
#define BF_DRAM_CTL18_INT_MASK_V(e)         BF_DRAM_CTL18_INT_MASK(BV_DRAM_CTL18_INT_MASK__##e)
#define BFM_DRAM_CTL18_INT_MASK_V(v)        BM_DRAM_CTL18_INT_MASK

#define HW_DRAM_CTL19                               HW(DRAM_CTL19)
#define HWA_DRAM_CTL19                              (0x800e0000 + 0x4c)
#define HWT_DRAM_CTL19                              HWIO_32_RW
#define HWN_DRAM_CTL19                              DRAM_CTL19
#define HWI_DRAM_CTL19                              
#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS          24
#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS          0xff000000
#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v)       (((v) & 0xff) << 24)
#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v)      BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS
#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS_V(e)     BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(BV_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS__##e)
#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS_V(v)    BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS
#define BP_DRAM_CTL19_DQS_OUT_SHIFT                 16
#define BM_DRAM_CTL19_DQS_OUT_SHIFT                 0x7f0000
#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v)              (((v) & 0x7f) << 16)
#define BFM_DRAM_CTL19_DQS_OUT_SHIFT(v)             BM_DRAM_CTL19_DQS_OUT_SHIFT
#define BF_DRAM_CTL19_DQS_OUT_SHIFT_V(e)            BF_DRAM_CTL19_DQS_OUT_SHIFT(BV_DRAM_CTL19_DQS_OUT_SHIFT__##e)
#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_V(v)           BM_DRAM_CTL19_DQS_OUT_SHIFT
#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1        8
#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1        0xff00
#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v)     (((v) & 0xff) << 8)
#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v)    BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1
#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1_V(e)   BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(BV_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1__##e)
#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1_V(v)  BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1
#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0        0
#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0        0xff
#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v)     (((v) & 0xff) << 0)
#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v)    BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0
#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0_V(e)   BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(BV_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0__##e)
#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0_V(v)  BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0

#define HW_DRAM_CTL20                           HW(DRAM_CTL20)
#define HWA_DRAM_CTL20                          (0x800e0000 + 0x50)
#define HWT_DRAM_CTL20                          HWIO_32_RW
#define HWN_DRAM_CTL20                          DRAM_CTL20
#define HWI_DRAM_CTL20                          
#define BP_DRAM_CTL20_TRCD_INT                  24
#define BM_DRAM_CTL20_TRCD_INT                  0xff000000
#define BF_DRAM_CTL20_TRCD_INT(v)               (((v) & 0xff) << 24)
#define BFM_DRAM_CTL20_TRCD_INT(v)              BM_DRAM_CTL20_TRCD_INT
#define BF_DRAM_CTL20_TRCD_INT_V(e)             BF_DRAM_CTL20_TRCD_INT(BV_DRAM_CTL20_TRCD_INT__##e)
#define BFM_DRAM_CTL20_TRCD_INT_V(v)            BM_DRAM_CTL20_TRCD_INT
#define BP_DRAM_CTL20_TRAS_MIN                  16
#define BM_DRAM_CTL20_TRAS_MIN                  0xff0000
#define BF_DRAM_CTL20_TRAS_MIN(v)               (((v) & 0xff) << 16)
#define BFM_DRAM_CTL20_TRAS_MIN(v)              BM_DRAM_CTL20_TRAS_MIN
#define BF_DRAM_CTL20_TRAS_MIN_V(e)             BF_DRAM_CTL20_TRAS_MIN(BV_DRAM_CTL20_TRAS_MIN__##e)
#define BFM_DRAM_CTL20_TRAS_MIN_V(v)            BM_DRAM_CTL20_TRAS_MIN
#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       8
#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       0xff00
#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v)    (((v) & 0xff) << 8)
#define BFM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v)   BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS
#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS_V(e)  BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(BV_DRAM_CTL20_WR_DQS_SHIFT_BYPASS__##e)
#define BFM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS_V(v) BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS
#define BP_DRAM_CTL20_WR_DQS_SHIFT              0
#define BM_DRAM_CTL20_WR_DQS_SHIFT              0x7f
#define BF_DRAM_CTL20_WR_DQS_SHIFT(v)           (((v) & 0x7f) << 0)
#define BFM_DRAM_CTL20_WR_DQS_SHIFT(v)          BM_DRAM_CTL20_WR_DQS_SHIFT
#define BF_DRAM_CTL20_WR_DQS_SHIFT_V(e)         BF_DRAM_CTL20_WR_DQS_SHIFT(BV_DRAM_CTL20_WR_DQS_SHIFT__##e)
#define BFM_DRAM_CTL20_WR_DQS_SHIFT_V(v)        BM_DRAM_CTL20_WR_DQS_SHIFT

#define HW_DRAM_CTL21                           HW(DRAM_CTL21)
#define HWA_DRAM_CTL21                          (0x800e0000 + 0x54)
#define HWT_DRAM_CTL21                          HWIO_32_RW
#define HWN_DRAM_CTL21                          DRAM_CTL21
#define HWI_DRAM_CTL21                          
#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH       8
#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH       0x3ff00
#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v)    (((v) & 0x3ff) << 8)
#define BFM_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v)   BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH
#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH_V(e)  BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(BV_DRAM_CTL21_OUT_OF_RANGE_LENGTH__##e)
#define BFM_DRAM_CTL21_OUT_OF_RANGE_LENGTH_V(v) BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH
#define BP_DRAM_CTL21_TRFC                      0
#define BM_DRAM_CTL21_TRFC                      0xff
#define BF_DRAM_CTL21_TRFC(v)                   (((v) & 0xff) << 0)
#define BFM_DRAM_CTL21_TRFC(v)                  BM_DRAM_CTL21_TRFC
#define BF_DRAM_CTL21_TRFC_V(e)                 BF_DRAM_CTL21_TRFC(BV_DRAM_CTL21_TRFC__##e)
#define BFM_DRAM_CTL21_TRFC_V(v)                BM_DRAM_CTL21_TRFC

#define HW_DRAM_CTL22                   HW(DRAM_CTL22)
#define HWA_DRAM_CTL22                  (0x800e0000 + 0x58)
#define HWT_DRAM_CTL22                  HWIO_32_RW
#define HWN_DRAM_CTL22                  DRAM_CTL22
#define HWI_DRAM_CTL22                  
#define BP_DRAM_CTL22_AHB0_WRCNT        16
#define BM_DRAM_CTL22_AHB0_WRCNT        0x7ff0000
#define BF_DRAM_CTL22_AHB0_WRCNT(v)     (((v) & 0x7ff) << 16)
#define BFM_DRAM_CTL22_AHB0_WRCNT(v)    BM_DRAM_CTL22_AHB0_WRCNT
#define BF_DRAM_CTL22_AHB0_WRCNT_V(e)   BF_DRAM_CTL22_AHB0_WRCNT(BV_DRAM_CTL22_AHB0_WRCNT__##e)
#define BFM_DRAM_CTL22_AHB0_WRCNT_V(v)  BM_DRAM_CTL22_AHB0_WRCNT
#define BP_DRAM_CTL22_AHB0_RDCNT        0
#define BM_DRAM_CTL22_AHB0_RDCNT        0x7ff
#define BF_DRAM_CTL22_AHB0_RDCNT(v)     (((v) & 0x7ff) << 0)
#define BFM_DRAM_CTL22_AHB0_RDCNT(v)    BM_DRAM_CTL22_AHB0_RDCNT
#define BF_DRAM_CTL22_AHB0_RDCNT_V(e)   BF_DRAM_CTL22_AHB0_RDCNT(BV_DRAM_CTL22_AHB0_RDCNT__##e)
#define BFM_DRAM_CTL22_AHB0_RDCNT_V(v)  BM_DRAM_CTL22_AHB0_RDCNT

#define HW_DRAM_CTL23                   HW(DRAM_CTL23)
#define HWA_DRAM_CTL23                  (0x800e0000 + 0x5c)
#define HWT_DRAM_CTL23                  HWIO_32_RW
#define HWN_DRAM_CTL23                  DRAM_CTL23
#define HWI_DRAM_CTL23                  
#define BP_DRAM_CTL23_AHB1_WRCNT        16
#define BM_DRAM_CTL23_AHB1_WRCNT        0x7ff0000
#define BF_DRAM_CTL23_AHB1_WRCNT(v)     (((v) & 0x7ff) << 16)
#define BFM_DRAM_CTL23_AHB1_WRCNT(v)    BM_DRAM_CTL23_AHB1_WRCNT
#define BF_DRAM_CTL23_AHB1_WRCNT_V(e)   BF_DRAM_CTL23_AHB1_WRCNT(BV_DRAM_CTL23_AHB1_WRCNT__##e)
#define BFM_DRAM_CTL23_AHB1_WRCNT_V(v)  BM_DRAM_CTL23_AHB1_WRCNT
#define BP_DRAM_CTL23_AHB1_RDCNT        0
#define BM_DRAM_CTL23_AHB1_RDCNT        0x7ff
#define BF_DRAM_CTL23_AHB1_RDCNT(v)     (((v) & 0x7ff) << 0)
#define BFM_DRAM_CTL23_AHB1_RDCNT(v)    BM_DRAM_CTL23_AHB1_RDCNT
#define BF_DRAM_CTL23_AHB1_RDCNT_V(e)   BF_DRAM_CTL23_AHB1_RDCNT(BV_DRAM_CTL23_AHB1_RDCNT__##e)
#define BFM_DRAM_CTL23_AHB1_RDCNT_V(v)  BM_DRAM_CTL23_AHB1_RDCNT

#define HW_DRAM_CTL24                   HW(DRAM_CTL24)
#define HWA_DRAM_CTL24                  (0x800e0000 + 0x60)
#define HWT_DRAM_CTL24                  HWIO_32_RW
#define HWN_DRAM_CTL24                  DRAM_CTL24
#define HWI_DRAM_CTL24                  
#define BP_DRAM_CTL24_AHB2_WRCNT        16
#define BM_DRAM_CTL24_AHB2_WRCNT        0x7ff0000
#define BF_DRAM_CTL24_AHB2_WRCNT(v)     (((v) & 0x7ff) << 16)
#define BFM_DRAM_CTL24_AHB2_WRCNT(v)    BM_DRAM_CTL24_AHB2_WRCNT
#define BF_DRAM_CTL24_AHB2_WRCNT_V(e)   BF_DRAM_CTL24_AHB2_WRCNT(BV_DRAM_CTL24_AHB2_WRCNT__##e)
#define BFM_DRAM_CTL24_AHB2_WRCNT_V(v)  BM_DRAM_CTL24_AHB2_WRCNT
#define BP_DRAM_CTL24_AHB2_RDCNT        0
#define BM_DRAM_CTL24_AHB2_RDCNT        0x7ff
#define BF_DRAM_CTL24_AHB2_RDCNT(v)     (((v) & 0x7ff) << 0)
#define BFM_DRAM_CTL24_AHB2_RDCNT(v)    BM_DRAM_CTL24_AHB2_RDCNT
#define BF_DRAM_CTL24_AHB2_RDCNT_V(e)   BF_DRAM_CTL24_AHB2_RDCNT(BV_DRAM_CTL24_AHB2_RDCNT__##e)
#define BFM_DRAM_CTL24_AHB2_RDCNT_V(v)  BM_DRAM_CTL24_AHB2_RDCNT

#define HW_DRAM_CTL25                   HW(DRAM_CTL25)
#define HWA_DRAM_CTL25                  (0x800e0000 + 0x64)
#define HWT_DRAM_CTL25                  HWIO_32_RW
#define HWN_DRAM_CTL25                  DRAM_CTL25
#define HWI_DRAM_CTL25                  
#define BP_DRAM_CTL25_AHB3_WRCNT        16
#define BM_DRAM_CTL25_AHB3_WRCNT        0x7ff0000
#define BF_DRAM_CTL25_AHB3_WRCNT(v)     (((v) & 0x7ff) << 16)
#define BFM_DRAM_CTL25_AHB3_WRCNT(v)    BM_DRAM_CTL25_AHB3_WRCNT
#define BF_DRAM_CTL25_AHB3_WRCNT_V(e)   BF_DRAM_CTL25_AHB3_WRCNT(BV_DRAM_CTL25_AHB3_WRCNT__##e)
#define BFM_DRAM_CTL25_AHB3_WRCNT_V(v)  BM_DRAM_CTL25_AHB3_WRCNT
#define BP_DRAM_CTL25_AHB3_RDCNT        0
#define BM_DRAM_CTL25_AHB3_RDCNT        0x7ff
#define BF_DRAM_CTL25_AHB3_RDCNT(v)     (((v) & 0x7ff) << 0)
#define BFM_DRAM_CTL25_AHB3_RDCNT(v)    BM_DRAM_CTL25_AHB3_RDCNT
#define BF_DRAM_CTL25_AHB3_RDCNT_V(e)   BF_DRAM_CTL25_AHB3_RDCNT(BV_DRAM_CTL25_AHB3_RDCNT__##e)
#define BFM_DRAM_CTL25_AHB3_RDCNT_V(v)  BM_DRAM_CTL25_AHB3_RDCNT

#define HW_DRAM_CTL26               HW(DRAM_CTL26)
#define HWA_DRAM_CTL26              (0x800e0000 + 0x68)
#define HWT_DRAM_CTL26              HWIO_32_RW
#define HWN_DRAM_CTL26              DRAM_CTL26
#define HWI_DRAM_CTL26              
#define BP_DRAM_CTL26_TREF          0
#define BM_DRAM_CTL26_TREF          0xfff
#define BF_DRAM_CTL26_TREF(v)       (((v) & 0xfff) << 0)
#define BFM_DRAM_CTL26_TREF(v)      BM_DRAM_CTL26_TREF
#define BF_DRAM_CTL26_TREF_V(e)     BF_DRAM_CTL26_TREF(BV_DRAM_CTL26_TREF__##e)
#define BFM_DRAM_CTL26_TREF_V(v)    BM_DRAM_CTL26_TREF

#define HW_DRAM_CTL27   HW(DRAM_CTL27)
#define HWA_DRAM_CTL27  (0x800e0000 + 0x6c)
#define HWT_DRAM_CTL27  HWIO_32_RW
#define HWN_DRAM_CTL27  DRAM_CTL27
#define HWI_DRAM_CTL27  

#define HW_DRAM_CTL28   HW(DRAM_CTL28)
#define HWA_DRAM_CTL28  (0x800e0000 + 0x70)
#define HWT_DRAM_CTL28  HWIO_32_RW
#define HWN_DRAM_CTL28  DRAM_CTL28
#define HWI_DRAM_CTL28  

#define HW_DRAM_CTL29                               HW(DRAM_CTL29)
#define HWA_DRAM_CTL29                              (0x800e0000 + 0x74)
#define HWT_DRAM_CTL29                              HWIO_32_RW
#define HWN_DRAM_CTL29                              DRAM_CTL29
#define HWI_DRAM_CTL29                              
#define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT         16
#define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT         0xffff0000
#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v)      (((v) & 0xffff) << 16)
#define BFM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v)     BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT
#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT_V(e)    BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(BV_DRAM_CTL29_LOWPOWER_INTERNAL_CNT__##e)
#define BFM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT_V(v)   BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT
#define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT         0
#define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT         0xffff
#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v)      (((v) & 0xffff) << 0)
#define BFM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v)     BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT
#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT_V(e)    BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(BV_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT__##e)
#define BFM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT_V(v)   BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT

#define HW_DRAM_CTL30                               HW(DRAM_CTL30)
#define HWA_DRAM_CTL30                              (0x800e0000 + 0x78)
#define HWT_DRAM_CTL30                              HWIO_32_RW
#define HWN_DRAM_CTL30                              DRAM_CTL30
#define HWI_DRAM_CTL30                              
#define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         16
#define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         0xffff0000
#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v)      (((v) & 0xffff) << 16)
#define BFM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v)     BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD
#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD_V(e)    BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(BV_DRAM_CTL30_LOWPOWER_REFRESH_HOLD__##e)
#define BFM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD_V(v)   BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD
#define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0
#define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0xffff
#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v)    (((v) & 0xffff) << 0)
#define BFM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v)   BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT
#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT_V(e)  BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(BV_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT__##e)
#define BFM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT_V(v) BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT

#define HW_DRAM_CTL31                                   HW(DRAM_CTL31)
#define HWA_DRAM_CTL31                                  (0x800e0000 + 0x7c)
#define HWT_DRAM_CTL31                                  HWIO_32_RW
#define HWN_DRAM_CTL31                                  DRAM_CTL31
#define HWI_DRAM_CTL31                                  
#define BP_DRAM_CTL31_TDLL                              16
#define BM_DRAM_CTL31_TDLL                              0xffff0000
#define BF_DRAM_CTL31_TDLL(v)                           (((v) & 0xffff) << 16)
#define BFM_DRAM_CTL31_TDLL(v)                          BM_DRAM_CTL31_TDLL
#define BF_DRAM_CTL31_TDLL_V(e)                         BF_DRAM_CTL31_TDLL(BV_DRAM_CTL31_TDLL__##e)
#define BFM_DRAM_CTL31_TDLL_V(v)                        BM_DRAM_CTL31_TDLL
#define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT         0
#define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT         0xffff
#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v)      (((v) & 0xffff) << 0)
#define BFM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v)     BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT
#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT_V(e)    BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(BV_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT__##e)
#define BFM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT_V(v)   BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT

#define HW_DRAM_CTL32                   HW(DRAM_CTL32)
#define HWA_DRAM_CTL32                  (0x800e0000 + 0x80)
#define HWT_DRAM_CTL32                  HWIO_32_RW
#define HWN_DRAM_CTL32                  DRAM_CTL32
#define HWI_DRAM_CTL32                  
#define BP_DRAM_CTL32_TXSNR             16
#define BM_DRAM_CTL32_TXSNR             0xffff0000
#define BF_DRAM_CTL32_TXSNR(v)          (((v) & 0xffff) << 16)
#define BFM_DRAM_CTL32_TXSNR(v)         BM_DRAM_CTL32_TXSNR
#define BF_DRAM_CTL32_TXSNR_V(e)        BF_DRAM_CTL32_TXSNR(BV_DRAM_CTL32_TXSNR__##e)
#define BFM_DRAM_CTL32_TXSNR_V(v)       BM_DRAM_CTL32_TXSNR
#define BP_DRAM_CTL32_TRAS_MAX          0
#define BM_DRAM_CTL32_TRAS_MAX          0xffff
#define BF_DRAM_CTL32_TRAS_MAX(v)       (((v) & 0xffff) << 0)
#define BFM_DRAM_CTL32_TRAS_MAX(v)      BM_DRAM_CTL32_TRAS_MAX
#define BF_DRAM_CTL32_TRAS_MAX_V(e)     BF_DRAM_CTL32_TRAS_MAX(BV_DRAM_CTL32_TRAS_MAX__##e)
#define BFM_DRAM_CTL32_TRAS_MAX_V(v)    BM_DRAM_CTL32_TRAS_MAX

#define HW_DRAM_CTL33               HW(DRAM_CTL33)
#define HWA_DRAM_CTL33              (0x800e0000 + 0x84)
#define HWT_DRAM_CTL33              HWIO_32_RW
#define HWN_DRAM_CTL33              DRAM_CTL33
#define HWI_DRAM_CTL33              
#define BP_DRAM_CTL33_VERSION       16
#define BM_DRAM_CTL33_VERSION       0xffff0000
#define BF_DRAM_CTL33_VERSION(v)    (((v) & 0xffff) << 16)
#define BFM_DRAM_CTL33_VERSION(v)   BM_DRAM_CTL33_VERSION
#define BF_DRAM_CTL33_VERSION_V(e)  BF_DRAM_CTL33_VERSION(BV_DRAM_CTL33_VERSION__##e)
#define BFM_DRAM_CTL33_VERSION_V(v) BM_DRAM_CTL33_VERSION
#define BP_DRAM_CTL33_TXSR          0
#define BM_DRAM_CTL33_TXSR          0xffff
#define BF_DRAM_CTL33_TXSR(v)       (((v) & 0xffff) << 0)
#define BFM_DRAM_CTL33_TXSR(v)      BM_DRAM_CTL33_TXSR
#define BF_DRAM_CTL33_TXSR_V(e)     BF_DRAM_CTL33_TXSR(BV_DRAM_CTL33_TXSR__##e)
#define BFM_DRAM_CTL33_TXSR_V(v)    BM_DRAM_CTL33_TXSR

#define HW_DRAM_CTL34               HW(DRAM_CTL34)
#define HWA_DRAM_CTL34              (0x800e0000 + 0x88)
#define HWT_DRAM_CTL34              HWIO_32_RW
#define HWN_DRAM_CTL34              DRAM_CTL34
#define HWI_DRAM_CTL34              
#define BP_DRAM_CTL34_TINIT         0
#define BM_DRAM_CTL34_TINIT         0xffffff
#define BF_DRAM_CTL34_TINIT(v)      (((v) & 0xffffff) << 0)
#define BFM_DRAM_CTL34_TINIT(v)     BM_DRAM_CTL34_TINIT
#define BF_DRAM_CTL34_TINIT_V(e)    BF_DRAM_CTL34_TINIT(BV_DRAM_CTL34_TINIT__##e)
#define BFM_DRAM_CTL34_TINIT_V(v)   BM_DRAM_CTL34_TINIT

#define HW_DRAM_CTL35                           HW(DRAM_CTL35)
#define HWA_DRAM_CTL35                          (0x800e0000 + 0x8c)
#define HWT_DRAM_CTL35                          HWIO_32_RW
#define HWN_DRAM_CTL35                          DRAM_CTL35
#define HWI_DRAM_CTL35                          
#define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR         0
#define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR         0x7fffffff
#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v)      (((v) & 0x7fffffff) << 0)
#define BFM_DRAM_CTL35_OUT_OF_RANGE_ADDR(v)     BM_DRAM_CTL35_OUT_OF_RANGE_ADDR
#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR_V(e)    BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(BV_DRAM_CTL35_OUT_OF_RANGE_ADDR__##e)
#define BFM_DRAM_CTL35_OUT_OF_RANGE_ADDR_V(v)   BM_DRAM_CTL35_OUT_OF_RANGE_ADDR

#define HW_DRAM_CTL36                               HW(DRAM_CTL36)
#define HWA_DRAM_CTL36                              (0x800e0000 + 0x90)
#define HWT_DRAM_CTL36                              HWIO_32_RW
#define HWN_DRAM_CTL36                              DRAM_CTL36
#define HWI_DRAM_CTL36                              
#define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT           24
#define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT           0x1000000
#define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v)        (((v) & 0x1) << 24)
#define BFM_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v)       BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT
#define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT_V(e)      BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(BV_DRAM_CTL36_PWRUP_SREFRESH_EXIT__##e)
#define BFM_DRAM_CTL36_PWRUP_SREFRESH_EXIT_V(v)     BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT
#define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH         16
#define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH         0x10000
#define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v)      (((v) & 0x1) << 16)
#define BFM_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v)     BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH
#define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH_V(e)    BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(BV_DRAM_CTL36_ENABLE_QUICK_SREFRESH__##e)
#define BFM_DRAM_CTL36_ENABLE_QUICK_SREFRESH_V(v)   BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH
#define BP_DRAM_CTL36_BUS_SHARE_ENABLE              8
#define BM_DRAM_CTL36_BUS_SHARE_ENABLE              0x100
#define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v)           (((v) & 0x1) << 8)
#define BFM_DRAM_CTL36_BUS_SHARE_ENABLE(v)          BM_DRAM_CTL36_BUS_SHARE_ENABLE
#define BF_DRAM_CTL36_BUS_SHARE_ENABLE_V(e)         BF_DRAM_CTL36_BUS_SHARE_ENABLE(BV_DRAM_CTL36_BUS_SHARE_ENABLE__##e)
#define BFM_DRAM_CTL36_BUS_SHARE_ENABLE_V(v)        BM_DRAM_CTL36_BUS_SHARE_ENABLE
#define BP_DRAM_CTL36_ACTIVE_AGING                  0
#define BM_DRAM_CTL36_ACTIVE_AGING                  0x1
#define BF_DRAM_CTL36_ACTIVE_AGING(v)               (((v) & 0x1) << 0)
#define BFM_DRAM_CTL36_ACTIVE_AGING(v)              BM_DRAM_CTL36_ACTIVE_AGING
#define BF_DRAM_CTL36_ACTIVE_AGING_V(e)             BF_DRAM_CTL36_ACTIVE_AGING(BV_DRAM_CTL36_ACTIVE_AGING__##e)
#define BFM_DRAM_CTL36_ACTIVE_AGING_V(v)            BM_DRAM_CTL36_ACTIVE_AGING

#define HW_DRAM_CTL37                           HW(DRAM_CTL37)
#define HWA_DRAM_CTL37                          (0x800e0000 + 0x94)
#define HWT_DRAM_CTL37                          HWIO_32_RW
#define HWN_DRAM_CTL37                          DRAM_CTL37
#define HWI_DRAM_CTL37                          
#define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT         8
#define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT         0x3ff00
#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v)      (((v) & 0x3ff) << 8)
#define BFM_DRAM_CTL37_BUS_SHARE_TIMEOUT(v)     BM_DRAM_CTL37_BUS_SHARE_TIMEOUT
#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT_V(e)    BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(BV_DRAM_CTL37_BUS_SHARE_TIMEOUT__##e)
#define BFM_DRAM_CTL37_BUS_SHARE_TIMEOUT_V(v)   BM_DRAM_CTL37_BUS_SHARE_TIMEOUT
#define BP_DRAM_CTL37_TREF_ENABLE               0
#define BM_DRAM_CTL37_TREF_ENABLE               0x1
#define BF_DRAM_CTL37_TREF_ENABLE(v)            (((v) & 0x1) << 0)
#define BFM_DRAM_CTL37_TREF_ENABLE(v)           BM_DRAM_CTL37_TREF_ENABLE
#define BF_DRAM_CTL37_TREF_ENABLE_V(e)          BF_DRAM_CTL37_TREF_ENABLE(BV_DRAM_CTL37_TREF_ENABLE__##e)
#define BFM_DRAM_CTL37_TREF_ENABLE_V(v)         BM_DRAM_CTL37_TREF_ENABLE

#define HW_DRAM_CTL38                       HW(DRAM_CTL38)
#define HWA_DRAM_CTL38                      (0x800e0000 + 0x98)
#define HWT_DRAM_CTL38                      HWIO_32_RW
#define HWN_DRAM_CTL38                      DRAM_CTL38
#define HWI_DRAM_CTL38                      
#define BP_DRAM_CTL38_EMRS2_DATA_0          16
#define BM_DRAM_CTL38_EMRS2_DATA_0          0x1fff0000
#define BF_DRAM_CTL38_EMRS2_DATA_0(v)       (((v) & 0x1fff) << 16)
#define BFM_DRAM_CTL38_EMRS2_DATA_0(v)      BM_DRAM_CTL38_EMRS2_DATA_0
#define BF_DRAM_CTL38_EMRS2_DATA_0_V(e)     BF_DRAM_CTL38_EMRS2_DATA_0(BV_DRAM_CTL38_EMRS2_DATA_0__##e)
#define BFM_DRAM_CTL38_EMRS2_DATA_0_V(v)    BM_DRAM_CTL38_EMRS2_DATA_0
#define BP_DRAM_CTL38_EMRS1_DATA            0
#define BM_DRAM_CTL38_EMRS1_DATA            0x1fff
#define BF_DRAM_CTL38_EMRS1_DATA(v)         (((v) & 0x1fff) << 0)
#define BFM_DRAM_CTL38_EMRS1_DATA(v)        BM_DRAM_CTL38_EMRS1_DATA
#define BF_DRAM_CTL38_EMRS1_DATA_V(e)       BF_DRAM_CTL38_EMRS1_DATA(BV_DRAM_CTL38_EMRS1_DATA__##e)
#define BFM_DRAM_CTL38_EMRS1_DATA_V(v)      BM_DRAM_CTL38_EMRS1_DATA

#define HW_DRAM_CTL39                       HW(DRAM_CTL39)
#define HWA_DRAM_CTL39                      (0x800e0000 + 0x9c)
#define HWT_DRAM_CTL39                      HWIO_32_RW
#define HWN_DRAM_CTL39                      DRAM_CTL39
#define HWI_DRAM_CTL39                      
#define BP_DRAM_CTL39_EMRS2_DATA_2          16
#define BM_DRAM_CTL39_EMRS2_DATA_2          0x1fff0000
#define BF_DRAM_CTL39_EMRS2_DATA_2(v)       (((v) & 0x1fff) << 16)
#define BFM_DRAM_CTL39_EMRS2_DATA_2(v)      BM_DRAM_CTL39_EMRS2_DATA_2
#define BF_DRAM_CTL39_EMRS2_DATA_2_V(e)     BF_DRAM_CTL39_EMRS2_DATA_2(BV_DRAM_CTL39_EMRS2_DATA_2__##e)
#define BFM_DRAM_CTL39_EMRS2_DATA_2_V(v)    BM_DRAM_CTL39_EMRS2_DATA_2
#define BP_DRAM_CTL39_EMRS2_DATA_1          0
#define BM_DRAM_CTL39_EMRS2_DATA_1          0x1fff
#define BF_DRAM_CTL39_EMRS2_DATA_1(v)       (((v) & 0x1fff) << 0)
#define BFM_DRAM_CTL39_EMRS2_DATA_1(v)      BM_DRAM_CTL39_EMRS2_DATA_1
#define BF_DRAM_CTL39_EMRS2_DATA_1_V(e)     BF_DRAM_CTL39_EMRS2_DATA_1(BV_DRAM_CTL39_EMRS2_DATA_1__##e)
#define BFM_DRAM_CTL39_EMRS2_DATA_1_V(v)    BM_DRAM_CTL39_EMRS2_DATA_1

#define HW_DRAM_CTL40                       HW(DRAM_CTL40)
#define HWA_DRAM_CTL40                      (0x800e0000 + 0xa0)
#define HWT_DRAM_CTL40                      HWIO_32_RW
#define HWN_DRAM_CTL40                      DRAM_CTL40
#define HWI_DRAM_CTL40                      
#define BP_DRAM_CTL40_TPDEX                 16
#define BM_DRAM_CTL40_TPDEX                 0xffff0000
#define BF_DRAM_CTL40_TPDEX(v)              (((v) & 0xffff) << 16)
#define BFM_DRAM_CTL40_TPDEX(v)             BM_DRAM_CTL40_TPDEX
#define BF_DRAM_CTL40_TPDEX_V(e)            BF_DRAM_CTL40_TPDEX(BV_DRAM_CTL40_TPDEX__##e)
#define BFM_DRAM_CTL40_TPDEX_V(v)           BM_DRAM_CTL40_TPDEX
#define BP_DRAM_CTL40_EMRS2_DATA_3          0
#define BM_DRAM_CTL40_EMRS2_DATA_3          0x1fff
#define BF_DRAM_CTL40_EMRS2_DATA_3(v)       (((v) & 0x1fff) << 0)
#define BFM_DRAM_CTL40_EMRS2_DATA_3(v)      BM_DRAM_CTL40_EMRS2_DATA_3
#define BF_DRAM_CTL40_EMRS2_DATA_3_V(e)     BF_DRAM_CTL40_EMRS2_DATA_3(BV_DRAM_CTL40_EMRS2_DATA_3__##e)
#define BFM_DRAM_CTL40_EMRS2_DATA_3_V(v)    BM_DRAM_CTL40_EMRS2_DATA_3

#endif /* __HEADERGEN_STMP3700_DRAM_H__*/
