/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * imx233 version: 2.4.0
 * imx233 authors: Amaury Pouly
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_IMX233_TVENC_H__
#define __HEADERGEN_IMX233_TVENC_H__

#define HW_TVENC_CTRL                                   HW(TVENC_CTRL)
#define HWA_TVENC_CTRL                                  (0x80038000 + 0x0)
#define HWT_TVENC_CTRL                                  HWIO_32_RW
#define HWN_TVENC_CTRL                                  TVENC_CTRL
#define HWI_TVENC_CTRL                                  
#define HW_TVENC_CTRL_SET                               HW(TVENC_CTRL_SET)
#define HWA_TVENC_CTRL_SET                              (HWA_TVENC_CTRL + 0x4)
#define HWT_TVENC_CTRL_SET                              HWIO_32_WO
#define HWN_TVENC_CTRL_SET                              TVENC_CTRL
#define HWI_TVENC_CTRL_SET                              
#define HW_TVENC_CTRL_CLR                               HW(TVENC_CTRL_CLR)
#define HWA_TVENC_CTRL_CLR                              (HWA_TVENC_CTRL + 0x8)
#define HWT_TVENC_CTRL_CLR                              HWIO_32_WO
#define HWN_TVENC_CTRL_CLR                              TVENC_CTRL
#define HWI_TVENC_CTRL_CLR                              
#define HW_TVENC_CTRL_TOG                               HW(TVENC_CTRL_TOG)
#define HWA_TVENC_CTRL_TOG                              (HWA_TVENC_CTRL + 0xc)
#define HWT_TVENC_CTRL_TOG                              HWIO_32_WO
#define HWN_TVENC_CTRL_TOG                              TVENC_CTRL
#define HWI_TVENC_CTRL_TOG                              
#define BP_TVENC_CTRL_SFTRST                            31
#define BM_TVENC_CTRL_SFTRST                            0x80000000
#define BF_TVENC_CTRL_SFTRST(v)                         (((v) & 0x1) << 31)
#define BFM_TVENC_CTRL_SFTRST(v)                        BM_TVENC_CTRL_SFTRST
#define BF_TVENC_CTRL_SFTRST_V(e)                       BF_TVENC_CTRL_SFTRST(BV_TVENC_CTRL_SFTRST__##e)
#define BFM_TVENC_CTRL_SFTRST_V(v)                      BM_TVENC_CTRL_SFTRST
#define BP_TVENC_CTRL_CLKGATE                           30
#define BM_TVENC_CTRL_CLKGATE                           0x40000000
#define BF_TVENC_CTRL_CLKGATE(v)                        (((v) & 0x1) << 30)
#define BFM_TVENC_CTRL_CLKGATE(v)                       BM_TVENC_CTRL_CLKGATE
#define BF_TVENC_CTRL_CLKGATE_V(e)                      BF_TVENC_CTRL_CLKGATE(BV_TVENC_CTRL_CLKGATE__##e)
#define BFM_TVENC_CTRL_CLKGATE_V(v)                     BM_TVENC_CTRL_CLKGATE
#define BP_TVENC_CTRL_TVENC_MACROVISION_PRESENT         29
#define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT         0x20000000
#define BF_TVENC_CTRL_TVENC_MACROVISION_PRESENT(v)      (((v) & 0x1) << 29)
#define BFM_TVENC_CTRL_TVENC_MACROVISION_PRESENT(v)     BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT
#define BF_TVENC_CTRL_TVENC_MACROVISION_PRESENT_V(e)    BF_TVENC_CTRL_TVENC_MACROVISION_PRESENT(BV_TVENC_CTRL_TVENC_MACROVISION_PRESENT__##e)
#define BFM_TVENC_CTRL_TVENC_MACROVISION_PRESENT_V(v)   BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT
#define BP_TVENC_CTRL_TVENC_COMPOSITE_PRESENT           28
#define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT           0x10000000
#define BF_TVENC_CTRL_TVENC_COMPOSITE_PRESENT(v)        (((v) & 0x1) << 28)
#define BFM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT(v)       BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT
#define BF_TVENC_CTRL_TVENC_COMPOSITE_PRESENT_V(e)      BF_TVENC_CTRL_TVENC_COMPOSITE_PRESENT(BV_TVENC_CTRL_TVENC_COMPOSITE_PRESENT__##e)
#define BFM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT_V(v)     BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT
#define BP_TVENC_CTRL_TVENC_SVIDEO_PRESENT              27
#define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT              0x8000000
#define BF_TVENC_CTRL_TVENC_SVIDEO_PRESENT(v)           (((v) & 0x1) << 27)
#define BFM_TVENC_CTRL_TVENC_SVIDEO_PRESENT(v)          BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT
#define BF_TVENC_CTRL_TVENC_SVIDEO_PRESENT_V(e)         BF_TVENC_CTRL_TVENC_SVIDEO_PRESENT(BV_TVENC_CTRL_TVENC_SVIDEO_PRESENT__##e)
#define BFM_TVENC_CTRL_TVENC_SVIDEO_PRESENT_V(v)        BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT
#define BP_TVENC_CTRL_TVENC_COMPONENT_PRESENT           26
#define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT           0x4000000
#define BF_TVENC_CTRL_TVENC_COMPONENT_PRESENT(v)        (((v) & 0x1) << 26)
#define BFM_TVENC_CTRL_TVENC_COMPONENT_PRESENT(v)       BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT
#define BF_TVENC_CTRL_TVENC_COMPONENT_PRESENT_V(e)      BF_TVENC_CTRL_TVENC_COMPONENT_PRESENT(BV_TVENC_CTRL_TVENC_COMPONENT_PRESENT__##e)
#define BFM_TVENC_CTRL_TVENC_COMPONENT_PRESENT_V(v)     BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT
#define BP_TVENC_CTRL_RSRVD1                            6
#define BM_TVENC_CTRL_RSRVD1                            0x3ffffc0
#define BF_TVENC_CTRL_RSRVD1(v)                         (((v) & 0xfffff) << 6)
#define BFM_TVENC_CTRL_RSRVD1(v)                        BM_TVENC_CTRL_RSRVD1
#define BF_TVENC_CTRL_RSRVD1_V(e)                       BF_TVENC_CTRL_RSRVD1(BV_TVENC_CTRL_RSRVD1__##e)
#define BFM_TVENC_CTRL_RSRVD1_V(v)                      BM_TVENC_CTRL_RSRVD1
#define BP_TVENC_CTRL_DAC_FIFO_NO_WRITE                 5
#define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE                 0x20
#define BF_TVENC_CTRL_DAC_FIFO_NO_WRITE(v)              (((v) & 0x1) << 5)
#define BFM_TVENC_CTRL_DAC_FIFO_NO_WRITE(v)             BM_TVENC_CTRL_DAC_FIFO_NO_WRITE
#define BF_TVENC_CTRL_DAC_FIFO_NO_WRITE_V(e)            BF_TVENC_CTRL_DAC_FIFO_NO_WRITE(BV_TVENC_CTRL_DAC_FIFO_NO_WRITE__##e)
#define BFM_TVENC_CTRL_DAC_FIFO_NO_WRITE_V(v)           BM_TVENC_CTRL_DAC_FIFO_NO_WRITE
#define BP_TVENC_CTRL_DAC_FIFO_NO_READ                  4
#define BM_TVENC_CTRL_DAC_FIFO_NO_READ                  0x10
#define BF_TVENC_CTRL_DAC_FIFO_NO_READ(v)               (((v) & 0x1) << 4)
#define BFM_TVENC_CTRL_DAC_FIFO_NO_READ(v)              BM_TVENC_CTRL_DAC_FIFO_NO_READ
#define BF_TVENC_CTRL_DAC_FIFO_NO_READ_V(e)             BF_TVENC_CTRL_DAC_FIFO_NO_READ(BV_TVENC_CTRL_DAC_FIFO_NO_READ__##e)
#define BFM_TVENC_CTRL_DAC_FIFO_NO_READ_V(v)            BM_TVENC_CTRL_DAC_FIFO_NO_READ
#define BP_TVENC_CTRL_DAC_DATA_FIFO_RST                 3
#define BM_TVENC_CTRL_DAC_DATA_FIFO_RST                 0x8
#define BF_TVENC_CTRL_DAC_DATA_FIFO_RST(v)              (((v) & 0x1) << 3)
#define BFM_TVENC_CTRL_DAC_DATA_FIFO_RST(v)             BM_TVENC_CTRL_DAC_DATA_FIFO_RST
#define BF_TVENC_CTRL_DAC_DATA_FIFO_RST_V(e)            BF_TVENC_CTRL_DAC_DATA_FIFO_RST(BV_TVENC_CTRL_DAC_DATA_FIFO_RST__##e)
#define BFM_TVENC_CTRL_DAC_DATA_FIFO_RST_V(v)           BM_TVENC_CTRL_DAC_DATA_FIFO_RST
#define BP_TVENC_CTRL_RSRVD2                            1
#define BM_TVENC_CTRL_RSRVD2                            0x6
#define BF_TVENC_CTRL_RSRVD2(v)                         (((v) & 0x3) << 1)
#define BFM_TVENC_CTRL_RSRVD2(v)                        BM_TVENC_CTRL_RSRVD2
#define BF_TVENC_CTRL_RSRVD2_V(e)                       BF_TVENC_CTRL_RSRVD2(BV_TVENC_CTRL_RSRVD2__##e)
#define BFM_TVENC_CTRL_RSRVD2_V(v)                      BM_TVENC_CTRL_RSRVD2
#define BP_TVENC_CTRL_DAC_MUX_MODE                      0
#define BM_TVENC_CTRL_DAC_MUX_MODE                      0x1
#define BF_TVENC_CTRL_DAC_MUX_MODE(v)                   (((v) & 0x1) << 0)
#define BFM_TVENC_CTRL_DAC_MUX_MODE(v)                  BM_TVENC_CTRL_DAC_MUX_MODE
#define BF_TVENC_CTRL_DAC_MUX_MODE_V(e)                 BF_TVENC_CTRL_DAC_MUX_MODE(BV_TVENC_CTRL_DAC_MUX_MODE__##e)
#define BFM_TVENC_CTRL_DAC_MUX_MODE_V(v)                BM_TVENC_CTRL_DAC_MUX_MODE

#define HW_TVENC_CONFIG                         HW(TVENC_CONFIG)
#define HWA_TVENC_CONFIG                        (0x80038000 + 0x10)
#define HWT_TVENC_CONFIG                        HWIO_32_RW
#define HWN_TVENC_CONFIG                        TVENC_CONFIG
#define HWI_TVENC_CONFIG                        
#define HW_TVENC_CONFIG_SET                     HW(TVENC_CONFIG_SET)
#define HWA_TVENC_CONFIG_SET                    (HWA_TVENC_CONFIG + 0x4)
#define HWT_TVENC_CONFIG_SET                    HWIO_32_WO
#define HWN_TVENC_CONFIG_SET                    TVENC_CONFIG
#define HWI_TVENC_CONFIG_SET                    
#define HW_TVENC_CONFIG_CLR                     HW(TVENC_CONFIG_CLR)
#define HWA_TVENC_CONFIG_CLR                    (HWA_TVENC_CONFIG + 0x8)
#define HWT_TVENC_CONFIG_CLR                    HWIO_32_WO
#define HWN_TVENC_CONFIG_CLR                    TVENC_CONFIG
#define HWI_TVENC_CONFIG_CLR                    
#define HW_TVENC_CONFIG_TOG                     HW(TVENC_CONFIG_TOG)
#define HWA_TVENC_CONFIG_TOG                    (HWA_TVENC_CONFIG + 0xc)
#define HWT_TVENC_CONFIG_TOG                    HWIO_32_WO
#define HWN_TVENC_CONFIG_TOG                    TVENC_CONFIG
#define HWI_TVENC_CONFIG_TOG                    
#define BP_TVENC_CONFIG_RSRVD5                  28
#define BM_TVENC_CONFIG_RSRVD5                  0xf0000000
#define BF_TVENC_CONFIG_RSRVD5(v)               (((v) & 0xf) << 28)
#define BFM_TVENC_CONFIG_RSRVD5(v)              BM_TVENC_CONFIG_RSRVD5
#define BF_TVENC_CONFIG_RSRVD5_V(e)             BF_TVENC_CONFIG_RSRVD5(BV_TVENC_CONFIG_RSRVD5__##e)
#define BFM_TVENC_CONFIG_RSRVD5_V(v)            BM_TVENC_CONFIG_RSRVD5
#define BP_TVENC_CONFIG_DEFAULT_PICFORM         27
#define BM_TVENC_CONFIG_DEFAULT_PICFORM         0x8000000
#define BF_TVENC_CONFIG_DEFAULT_PICFORM(v)      (((v) & 0x1) << 27)
#define BFM_TVENC_CONFIG_DEFAULT_PICFORM(v)     BM_TVENC_CONFIG_DEFAULT_PICFORM
#define BF_TVENC_CONFIG_DEFAULT_PICFORM_V(e)    BF_TVENC_CONFIG_DEFAULT_PICFORM(BV_TVENC_CONFIG_DEFAULT_PICFORM__##e)
#define BFM_TVENC_CONFIG_DEFAULT_PICFORM_V(v)   BM_TVENC_CONFIG_DEFAULT_PICFORM
#define BP_TVENC_CONFIG_YDEL_ADJ                24
#define BM_TVENC_CONFIG_YDEL_ADJ                0x7000000
#define BF_TVENC_CONFIG_YDEL_ADJ(v)             (((v) & 0x7) << 24)
#define BFM_TVENC_CONFIG_YDEL_ADJ(v)            BM_TVENC_CONFIG_YDEL_ADJ
#define BF_TVENC_CONFIG_YDEL_ADJ_V(e)           BF_TVENC_CONFIG_YDEL_ADJ(BV_TVENC_CONFIG_YDEL_ADJ__##e)
#define BFM_TVENC_CONFIG_YDEL_ADJ_V(v)          BM_TVENC_CONFIG_YDEL_ADJ
#define BP_TVENC_CONFIG_RSRVD4                  23
#define BM_TVENC_CONFIG_RSRVD4                  0x800000
#define BF_TVENC_CONFIG_RSRVD4(v)               (((v) & 0x1) << 23)
#define BFM_TVENC_CONFIG_RSRVD4(v)              BM_TVENC_CONFIG_RSRVD4
#define BF_TVENC_CONFIG_RSRVD4_V(e)             BF_TVENC_CONFIG_RSRVD4(BV_TVENC_CONFIG_RSRVD4__##e)
#define BFM_TVENC_CONFIG_RSRVD4_V(v)            BM_TVENC_CONFIG_RSRVD4
#define BP_TVENC_CONFIG_RSRVD3                  22
#define BM_TVENC_CONFIG_RSRVD3                  0x400000
#define BF_TVENC_CONFIG_RSRVD3(v)               (((v) & 0x1) << 22)
#define BFM_TVENC_CONFIG_RSRVD3(v)              BM_TVENC_CONFIG_RSRVD3
#define BF_TVENC_CONFIG_RSRVD3_V(e)             BF_TVENC_CONFIG_RSRVD3(BV_TVENC_CONFIG_RSRVD3__##e)
#define BFM_TVENC_CONFIG_RSRVD3_V(v)            BM_TVENC_CONFIG_RSRVD3
#define BP_TVENC_CONFIG_ADD_YPBPR_PED           21
#define BM_TVENC_CONFIG_ADD_YPBPR_PED           0x200000
#define BF_TVENC_CONFIG_ADD_YPBPR_PED(v)        (((v) & 0x1) << 21)
#define BFM_TVENC_CONFIG_ADD_YPBPR_PED(v)       BM_TVENC_CONFIG_ADD_YPBPR_PED
#define BF_TVENC_CONFIG_ADD_YPBPR_PED_V(e)      BF_TVENC_CONFIG_ADD_YPBPR_PED(BV_TVENC_CONFIG_ADD_YPBPR_PED__##e)
#define BFM_TVENC_CONFIG_ADD_YPBPR_PED_V(v)     BM_TVENC_CONFIG_ADD_YPBPR_PED
#define BP_TVENC_CONFIG_PAL_SHAPE               20
#define BM_TVENC_CONFIG_PAL_SHAPE               0x100000
#define BF_TVENC_CONFIG_PAL_SHAPE(v)            (((v) & 0x1) << 20)
#define BFM_TVENC_CONFIG_PAL_SHAPE(v)           BM_TVENC_CONFIG_PAL_SHAPE
#define BF_TVENC_CONFIG_PAL_SHAPE_V(e)          BF_TVENC_CONFIG_PAL_SHAPE(BV_TVENC_CONFIG_PAL_SHAPE__##e)
#define BFM_TVENC_CONFIG_PAL_SHAPE_V(v)         BM_TVENC_CONFIG_PAL_SHAPE
#define BP_TVENC_CONFIG_NO_PED                  19
#define BM_TVENC_CONFIG_NO_PED                  0x80000
#define BF_TVENC_CONFIG_NO_PED(v)               (((v) & 0x1) << 19)
#define BFM_TVENC_CONFIG_NO_PED(v)              BM_TVENC_CONFIG_NO_PED
#define BF_TVENC_CONFIG_NO_PED_V(e)             BF_TVENC_CONFIG_NO_PED(BV_TVENC_CONFIG_NO_PED__##e)
#define BFM_TVENC_CONFIG_NO_PED_V(v)            BM_TVENC_CONFIG_NO_PED
#define BP_TVENC_CONFIG_COLOR_BAR_EN            18
#define BM_TVENC_CONFIG_COLOR_BAR_EN            0x40000
#define BF_TVENC_CONFIG_COLOR_BAR_EN(v)         (((v) & 0x1) << 18)
#define BFM_TVENC_CONFIG_COLOR_BAR_EN(v)        BM_TVENC_CONFIG_COLOR_BAR_EN
#define BF_TVENC_CONFIG_COLOR_BAR_EN_V(e)       BF_TVENC_CONFIG_COLOR_BAR_EN(BV_TVENC_CONFIG_COLOR_BAR_EN__##e)
#define BFM_TVENC_CONFIG_COLOR_BAR_EN_V(v)      BM_TVENC_CONFIG_COLOR_BAR_EN
#define BP_TVENC_CONFIG_YGAIN_SEL               16
#define BM_TVENC_CONFIG_YGAIN_SEL               0x30000
#define BF_TVENC_CONFIG_YGAIN_SEL(v)            (((v) & 0x3) << 16)
#define BFM_TVENC_CONFIG_YGAIN_SEL(v)           BM_TVENC_CONFIG_YGAIN_SEL
#define BF_TVENC_CONFIG_YGAIN_SEL_V(e)          BF_TVENC_CONFIG_YGAIN_SEL(BV_TVENC_CONFIG_YGAIN_SEL__##e)
#define BFM_TVENC_CONFIG_YGAIN_SEL_V(v)         BM_TVENC_CONFIG_YGAIN_SEL
#define BP_TVENC_CONFIG_CGAIN                   14
#define BM_TVENC_CONFIG_CGAIN                   0xc000
#define BF_TVENC_CONFIG_CGAIN(v)                (((v) & 0x3) << 14)
#define BFM_TVENC_CONFIG_CGAIN(v)               BM_TVENC_CONFIG_CGAIN
#define BF_TVENC_CONFIG_CGAIN_V(e)              BF_TVENC_CONFIG_CGAIN(BV_TVENC_CONFIG_CGAIN__##e)
#define BFM_TVENC_CONFIG_CGAIN_V(v)             BM_TVENC_CONFIG_CGAIN
#define BP_TVENC_CONFIG_CLK_PHS                 12
#define BM_TVENC_CONFIG_CLK_PHS                 0x3000
#define BF_TVENC_CONFIG_CLK_PHS(v)              (((v) & 0x3) << 12)
#define BFM_TVENC_CONFIG_CLK_PHS(v)             BM_TVENC_CONFIG_CLK_PHS
#define BF_TVENC_CONFIG_CLK_PHS_V(e)            BF_TVENC_CONFIG_CLK_PHS(BV_TVENC_CONFIG_CLK_PHS__##e)
#define BFM_TVENC_CONFIG_CLK_PHS_V(v)           BM_TVENC_CONFIG_CLK_PHS
#define BP_TVENC_CONFIG_RSRVD2                  11
#define BM_TVENC_CONFIG_RSRVD2                  0x800
#define BF_TVENC_CONFIG_RSRVD2(v)               (((v) & 0x1) << 11)
#define BFM_TVENC_CONFIG_RSRVD2(v)              BM_TVENC_CONFIG_RSRVD2
#define BF_TVENC_CONFIG_RSRVD2_V(e)             BF_TVENC_CONFIG_RSRVD2(BV_TVENC_CONFIG_RSRVD2__##e)
#define BFM_TVENC_CONFIG_RSRVD2_V(v)            BM_TVENC_CONFIG_RSRVD2
#define BP_TVENC_CONFIG_FSYNC_ENBL              10
#define BM_TVENC_CONFIG_FSYNC_ENBL              0x400
#define BF_TVENC_CONFIG_FSYNC_ENBL(v)           (((v) & 0x1) << 10)
#define BFM_TVENC_CONFIG_FSYNC_ENBL(v)          BM_TVENC_CONFIG_FSYNC_ENBL
#define BF_TVENC_CONFIG_FSYNC_ENBL_V(e)         BF_TVENC_CONFIG_FSYNC_ENBL(BV_TVENC_CONFIG_FSYNC_ENBL__##e)
#define BFM_TVENC_CONFIG_FSYNC_ENBL_V(v)        BM_TVENC_CONFIG_FSYNC_ENBL
#define BP_TVENC_CONFIG_FSYNC_PHS               9
#define BM_TVENC_CONFIG_FSYNC_PHS               0x200
#define BF_TVENC_CONFIG_FSYNC_PHS(v)            (((v) & 0x1) << 9)
#define BFM_TVENC_CONFIG_FSYNC_PHS(v)           BM_TVENC_CONFIG_FSYNC_PHS
#define BF_TVENC_CONFIG_FSYNC_PHS_V(e)          BF_TVENC_CONFIG_FSYNC_PHS(BV_TVENC_CONFIG_FSYNC_PHS__##e)
#define BFM_TVENC_CONFIG_FSYNC_PHS_V(v)         BM_TVENC_CONFIG_FSYNC_PHS
#define BP_TVENC_CONFIG_HSYNC_PHS               8
#define BM_TVENC_CONFIG_HSYNC_PHS               0x100
#define BF_TVENC_CONFIG_HSYNC_PHS(v)            (((v) & 0x1) << 8)
#define BFM_TVENC_CONFIG_HSYNC_PHS(v)           BM_TVENC_CONFIG_HSYNC_PHS
#define BF_TVENC_CONFIG_HSYNC_PHS_V(e)          BF_TVENC_CONFIG_HSYNC_PHS(BV_TVENC_CONFIG_HSYNC_PHS__##e)
#define BFM_TVENC_CONFIG_HSYNC_PHS_V(v)         BM_TVENC_CONFIG_HSYNC_PHS
#define BP_TVENC_CONFIG_VSYNC_PHS               7
#define BM_TVENC_CONFIG_VSYNC_PHS               0x80
#define BF_TVENC_CONFIG_VSYNC_PHS(v)            (((v) & 0x1) << 7)
#define BFM_TVENC_CONFIG_VSYNC_PHS(v)           BM_TVENC_CONFIG_VSYNC_PHS
#define BF_TVENC_CONFIG_VSYNC_PHS_V(e)          BF_TVENC_CONFIG_VSYNC_PHS(BV_TVENC_CONFIG_VSYNC_PHS__##e)
#define BFM_TVENC_CONFIG_VSYNC_PHS_V(v)         BM_TVENC_CONFIG_VSYNC_PHS
#define BP_TVENC_CONFIG_SYNC_MODE               4
#define BM_TVENC_CONFIG_SYNC_MODE               0x70
#define BF_TVENC_CONFIG_SYNC_MODE(v)            (((v) & 0x7) << 4)
#define BFM_TVENC_CONFIG_SYNC_MODE(v)           BM_TVENC_CONFIG_SYNC_MODE
#define BF_TVENC_CONFIG_SYNC_MODE_V(e)          BF_TVENC_CONFIG_SYNC_MODE(BV_TVENC_CONFIG_SYNC_MODE__##e)
#define BFM_TVENC_CONFIG_SYNC_MODE_V(v)         BM_TVENC_CONFIG_SYNC_MODE
#define BP_TVENC_CONFIG_RSRVD1                  3
#define BM_TVENC_CONFIG_RSRVD1                  0x8
#define BF_TVENC_CONFIG_RSRVD1(v)               (((v) & 0x1) << 3)
#define BFM_TVENC_CONFIG_RSRVD1(v)              BM_TVENC_CONFIG_RSRVD1
#define BF_TVENC_CONFIG_RSRVD1_V(e)             BF_TVENC_CONFIG_RSRVD1(BV_TVENC_CONFIG_RSRVD1__##e)
#define BFM_TVENC_CONFIG_RSRVD1_V(v)            BM_TVENC_CONFIG_RSRVD1
#define BP_TVENC_CONFIG_ENCD_MODE               0
#define BM_TVENC_CONFIG_ENCD_MODE               0x7
#define BF_TVENC_CONFIG_ENCD_MODE(v)            (((v) & 0x7) << 0)
#define BFM_TVENC_CONFIG_ENCD_MODE(v)           BM_TVENC_CONFIG_ENCD_MODE
#define BF_TVENC_CONFIG_ENCD_MODE_V(e)          BF_TVENC_CONFIG_ENCD_MODE(BV_TVENC_CONFIG_ENCD_MODE__##e)
#define BFM_TVENC_CONFIG_ENCD_MODE_V(v)         BM_TVENC_CONFIG_ENCD_MODE

#define HW_TVENC_FILTCTRL                       HW(TVENC_FILTCTRL)
#define HWA_TVENC_FILTCTRL                      (0x80038000 + 0x20)
#define HWT_TVENC_FILTCTRL                      HWIO_32_RW
#define HWN_TVENC_FILTCTRL                      TVENC_FILTCTRL
#define HWI_TVENC_FILTCTRL                      
#define HW_TVENC_FILTCTRL_SET                   HW(TVENC_FILTCTRL_SET)
#define HWA_TVENC_FILTCTRL_SET                  (HWA_TVENC_FILTCTRL + 0x4)
#define HWT_TVENC_FILTCTRL_SET                  HWIO_32_WO
#define HWN_TVENC_FILTCTRL_SET                  TVENC_FILTCTRL
#define HWI_TVENC_FILTCTRL_SET                  
#define HW_TVENC_FILTCTRL_CLR                   HW(TVENC_FILTCTRL_CLR)
#define HWA_TVENC_FILTCTRL_CLR                  (HWA_TVENC_FILTCTRL + 0x8)
#define HWT_TVENC_FILTCTRL_CLR                  HWIO_32_WO
#define HWN_TVENC_FILTCTRL_CLR                  TVENC_FILTCTRL
#define HWI_TVENC_FILTCTRL_CLR                  
#define HW_TVENC_FILTCTRL_TOG                   HW(TVENC_FILTCTRL_TOG)
#define HWA_TVENC_FILTCTRL_TOG                  (HWA_TVENC_FILTCTRL + 0xc)
#define HWT_TVENC_FILTCTRL_TOG                  HWIO_32_WO
#define HWN_TVENC_FILTCTRL_TOG                  TVENC_FILTCTRL
#define HWI_TVENC_FILTCTRL_TOG                  
#define BP_TVENC_FILTCTRL_RSRVD1                20
#define BM_TVENC_FILTCTRL_RSRVD1                0xfff00000
#define BF_TVENC_FILTCTRL_RSRVD1(v)             (((v) & 0xfff) << 20)
#define BFM_TVENC_FILTCTRL_RSRVD1(v)            BM_TVENC_FILTCTRL_RSRVD1
#define BF_TVENC_FILTCTRL_RSRVD1_V(e)           BF_TVENC_FILTCTRL_RSRVD1(BV_TVENC_FILTCTRL_RSRVD1__##e)
#define BFM_TVENC_FILTCTRL_RSRVD1_V(v)          BM_TVENC_FILTCTRL_RSRVD1
#define BP_TVENC_FILTCTRL_YSHARP_BW             19
#define BM_TVENC_FILTCTRL_YSHARP_BW             0x80000
#define BF_TVENC_FILTCTRL_YSHARP_BW(v)          (((v) & 0x1) << 19)
#define BFM_TVENC_FILTCTRL_YSHARP_BW(v)         BM_TVENC_FILTCTRL_YSHARP_BW
#define BF_TVENC_FILTCTRL_YSHARP_BW_V(e)        BF_TVENC_FILTCTRL_YSHARP_BW(BV_TVENC_FILTCTRL_YSHARP_BW__##e)
#define BFM_TVENC_FILTCTRL_YSHARP_BW_V(v)       BM_TVENC_FILTCTRL_YSHARP_BW
#define BP_TVENC_FILTCTRL_YD_OFFSETSEL          18
#define BM_TVENC_FILTCTRL_YD_OFFSETSEL          0x40000
#define BF_TVENC_FILTCTRL_YD_OFFSETSEL(v)       (((v) & 0x1) << 18)
#define BFM_TVENC_FILTCTRL_YD_OFFSETSEL(v)      BM_TVENC_FILTCTRL_YD_OFFSETSEL
#define BF_TVENC_FILTCTRL_YD_OFFSETSEL_V(e)     BF_TVENC_FILTCTRL_YD_OFFSETSEL(BV_TVENC_FILTCTRL_YD_OFFSETSEL__##e)
#define BFM_TVENC_FILTCTRL_YD_OFFSETSEL_V(v)    BM_TVENC_FILTCTRL_YD_OFFSETSEL
#define BP_TVENC_FILTCTRL_SEL_YLPF              17
#define BM_TVENC_FILTCTRL_SEL_YLPF              0x20000
#define BF_TVENC_FILTCTRL_SEL_YLPF(v)           (((v) & 0x1) << 17)
#define BFM_TVENC_FILTCTRL_SEL_YLPF(v)          BM_TVENC_FILTCTRL_SEL_YLPF
#define BF_TVENC_FILTCTRL_SEL_YLPF_V(e)         BF_TVENC_FILTCTRL_SEL_YLPF(BV_TVENC_FILTCTRL_SEL_YLPF__##e)
#define BFM_TVENC_FILTCTRL_SEL_YLPF_V(v)        BM_TVENC_FILTCTRL_SEL_YLPF
#define BP_TVENC_FILTCTRL_SEL_CLPF              16
#define BM_TVENC_FILTCTRL_SEL_CLPF              0x10000
#define BF_TVENC_FILTCTRL_SEL_CLPF(v)           (((v) & 0x1) << 16)
#define BFM_TVENC_FILTCTRL_SEL_CLPF(v)          BM_TVENC_FILTCTRL_SEL_CLPF
#define BF_TVENC_FILTCTRL_SEL_CLPF_V(e)         BF_TVENC_FILTCTRL_SEL_CLPF(BV_TVENC_FILTCTRL_SEL_CLPF__##e)
#define BFM_TVENC_FILTCTRL_SEL_CLPF_V(v)        BM_TVENC_FILTCTRL_SEL_CLPF
#define BP_TVENC_FILTCTRL_SEL_YSHARP            15
#define BM_TVENC_FILTCTRL_SEL_YSHARP            0x8000
#define BF_TVENC_FILTCTRL_SEL_YSHARP(v)         (((v) & 0x1) << 15)
#define BFM_TVENC_FILTCTRL_SEL_YSHARP(v)        BM_TVENC_FILTCTRL_SEL_YSHARP
#define BF_TVENC_FILTCTRL_SEL_YSHARP_V(e)       BF_TVENC_FILTCTRL_SEL_YSHARP(BV_TVENC_FILTCTRL_SEL_YSHARP__##e)
#define BFM_TVENC_FILTCTRL_SEL_YSHARP_V(v)      BM_TVENC_FILTCTRL_SEL_YSHARP
#define BP_TVENC_FILTCTRL_YLPF_COEFSEL          14
#define BM_TVENC_FILTCTRL_YLPF_COEFSEL          0x4000
#define BF_TVENC_FILTCTRL_YLPF_COEFSEL(v)       (((v) & 0x1) << 14)
#define BFM_TVENC_FILTCTRL_YLPF_COEFSEL(v)      BM_TVENC_FILTCTRL_YLPF_COEFSEL
#define BF_TVENC_FILTCTRL_YLPF_COEFSEL_V(e)     BF_TVENC_FILTCTRL_YLPF_COEFSEL(BV_TVENC_FILTCTRL_YLPF_COEFSEL__##e)
#define BFM_TVENC_FILTCTRL_YLPF_COEFSEL_V(v)    BM_TVENC_FILTCTRL_YLPF_COEFSEL
#define BP_TVENC_FILTCTRL_COEFSEL_CLPF          13
#define BM_TVENC_FILTCTRL_COEFSEL_CLPF          0x2000
#define BF_TVENC_FILTCTRL_COEFSEL_CLPF(v)       (((v) & 0x1) << 13)
#define BFM_TVENC_FILTCTRL_COEFSEL_CLPF(v)      BM_TVENC_FILTCTRL_COEFSEL_CLPF
#define BF_TVENC_FILTCTRL_COEFSEL_CLPF_V(e)     BF_TVENC_FILTCTRL_COEFSEL_CLPF(BV_TVENC_FILTCTRL_COEFSEL_CLPF__##e)
#define BFM_TVENC_FILTCTRL_COEFSEL_CLPF_V(v)    BM_TVENC_FILTCTRL_COEFSEL_CLPF
#define BP_TVENC_FILTCTRL_YS_GAINSGN            12
#define BM_TVENC_FILTCTRL_YS_GAINSGN            0x1000
#define BF_TVENC_FILTCTRL_YS_GAINSGN(v)         (((v) & 0x1) << 12)
#define BFM_TVENC_FILTCTRL_YS_GAINSGN(v)        BM_TVENC_FILTCTRL_YS_GAINSGN
#define BF_TVENC_FILTCTRL_YS_GAINSGN_V(e)       BF_TVENC_FILTCTRL_YS_GAINSGN(BV_TVENC_FILTCTRL_YS_GAINSGN__##e)
#define BFM_TVENC_FILTCTRL_YS_GAINSGN_V(v)      BM_TVENC_FILTCTRL_YS_GAINSGN
#define BP_TVENC_FILTCTRL_YS_GAINSEL            10
#define BM_TVENC_FILTCTRL_YS_GAINSEL            0xc00
#define BF_TVENC_FILTCTRL_YS_GAINSEL(v)         (((v) & 0x3) << 10)
#define BFM_TVENC_FILTCTRL_YS_GAINSEL(v)        BM_TVENC_FILTCTRL_YS_GAINSEL
#define BF_TVENC_FILTCTRL_YS_GAINSEL_V(e)       BF_TVENC_FILTCTRL_YS_GAINSEL(BV_TVENC_FILTCTRL_YS_GAINSEL__##e)
#define BFM_TVENC_FILTCTRL_YS_GAINSEL_V(v)      BM_TVENC_FILTCTRL_YS_GAINSEL
#define BP_TVENC_FILTCTRL_RSRVD2                9
#define BM_TVENC_FILTCTRL_RSRVD2                0x200
#define BF_TVENC_FILTCTRL_RSRVD2(v)             (((v) & 0x1) << 9)
#define BFM_TVENC_FILTCTRL_RSRVD2(v)            BM_TVENC_FILTCTRL_RSRVD2
#define BF_TVENC_FILTCTRL_RSRVD2_V(e)           BF_TVENC_FILTCTRL_RSRVD2(BV_TVENC_FILTCTRL_RSRVD2__##e)
#define BFM_TVENC_FILTCTRL_RSRVD2_V(v)          BM_TVENC_FILTCTRL_RSRVD2
#define BP_TVENC_FILTCTRL_RSRVD3                8
#define BM_TVENC_FILTCTRL_RSRVD3                0x100
#define BF_TVENC_FILTCTRL_RSRVD3(v)             (((v) & 0x1) << 8)
#define BFM_TVENC_FILTCTRL_RSRVD3(v)            BM_TVENC_FILTCTRL_RSRVD3
#define BF_TVENC_FILTCTRL_RSRVD3_V(e)           BF_TVENC_FILTCTRL_RSRVD3(BV_TVENC_FILTCTRL_RSRVD3__##e)
#define BFM_TVENC_FILTCTRL_RSRVD3_V(v)          BM_TVENC_FILTCTRL_RSRVD3
#define BP_TVENC_FILTCTRL_RSRVD4                0
#define BM_TVENC_FILTCTRL_RSRVD4                0xff
#define BF_TVENC_FILTCTRL_RSRVD4(v)             (((v) & 0xff) << 0)
#define BFM_TVENC_FILTCTRL_RSRVD4(v)            BM_TVENC_FILTCTRL_RSRVD4
#define BF_TVENC_FILTCTRL_RSRVD4_V(e)           BF_TVENC_FILTCTRL_RSRVD4(BV_TVENC_FILTCTRL_RSRVD4__##e)
#define BFM_TVENC_FILTCTRL_RSRVD4_V(v)          BM_TVENC_FILTCTRL_RSRVD4

#define HW_TVENC_SYNCOFFSET                 HW(TVENC_SYNCOFFSET)
#define HWA_TVENC_SYNCOFFSET                (0x80038000 + 0x30)
#define HWT_TVENC_SYNCOFFSET                HWIO_32_RW
#define HWN_TVENC_SYNCOFFSET                TVENC_SYNCOFFSET
#define HWI_TVENC_SYNCOFFSET                
#define HW_TVENC_SYNCOFFSET_SET             HW(TVENC_SYNCOFFSET_SET)
#define HWA_TVENC_SYNCOFFSET_SET            (HWA_TVENC_SYNCOFFSET + 0x4)
#define HWT_TVENC_SYNCOFFSET_SET            HWIO_32_WO
#define HWN_TVENC_SYNCOFFSET_SET            TVENC_SYNCOFFSET
#define HWI_TVENC_SYNCOFFSET_SET            
#define HW_TVENC_SYNCOFFSET_CLR             HW(TVENC_SYNCOFFSET_CLR)
#define HWA_TVENC_SYNCOFFSET_CLR            (HWA_TVENC_SYNCOFFSET + 0x8)
#define HWT_TVENC_SYNCOFFSET_CLR            HWIO_32_WO
#define HWN_TVENC_SYNCOFFSET_CLR            TVENC_SYNCOFFSET
#define HWI_TVENC_SYNCOFFSET_CLR            
#define HW_TVENC_SYNCOFFSET_TOG             HW(TVENC_SYNCOFFSET_TOG)
#define HWA_TVENC_SYNCOFFSET_TOG            (HWA_TVENC_SYNCOFFSET + 0xc)
#define HWT_TVENC_SYNCOFFSET_TOG            HWIO_32_WO
#define HWN_TVENC_SYNCOFFSET_TOG            TVENC_SYNCOFFSET
#define HWI_TVENC_SYNCOFFSET_TOG            
#define BP_TVENC_SYNCOFFSET_RSRVD1          31
#define BM_TVENC_SYNCOFFSET_RSRVD1          0x80000000
#define BF_TVENC_SYNCOFFSET_RSRVD1(v)       (((v) & 0x1) << 31)
#define BFM_TVENC_SYNCOFFSET_RSRVD1(v)      BM_TVENC_SYNCOFFSET_RSRVD1
#define BF_TVENC_SYNCOFFSET_RSRVD1_V(e)     BF_TVENC_SYNCOFFSET_RSRVD1(BV_TVENC_SYNCOFFSET_RSRVD1__##e)
#define BFM_TVENC_SYNCOFFSET_RSRVD1_V(v)    BM_TVENC_SYNCOFFSET_RSRVD1
#define BP_TVENC_SYNCOFFSET_HSO             20
#define BM_TVENC_SYNCOFFSET_HSO             0x7ff00000
#define BF_TVENC_SYNCOFFSET_HSO(v)          (((v) & 0x7ff) << 20)
#define BFM_TVENC_SYNCOFFSET_HSO(v)         BM_TVENC_SYNCOFFSET_HSO
#define BF_TVENC_SYNCOFFSET_HSO_V(e)        BF_TVENC_SYNCOFFSET_HSO(BV_TVENC_SYNCOFFSET_HSO__##e)
#define BFM_TVENC_SYNCOFFSET_HSO_V(v)       BM_TVENC_SYNCOFFSET_HSO
#define BP_TVENC_SYNCOFFSET_VSO             10
#define BM_TVENC_SYNCOFFSET_VSO             0xffc00
#define BF_TVENC_SYNCOFFSET_VSO(v)          (((v) & 0x3ff) << 10)
#define BFM_TVENC_SYNCOFFSET_VSO(v)         BM_TVENC_SYNCOFFSET_VSO
#define BF_TVENC_SYNCOFFSET_VSO_V(e)        BF_TVENC_SYNCOFFSET_VSO(BV_TVENC_SYNCOFFSET_VSO__##e)
#define BFM_TVENC_SYNCOFFSET_VSO_V(v)       BM_TVENC_SYNCOFFSET_VSO
#define BP_TVENC_SYNCOFFSET_HLC             0
#define BM_TVENC_SYNCOFFSET_HLC             0x3ff
#define BF_TVENC_SYNCOFFSET_HLC(v)          (((v) & 0x3ff) << 0)
#define BFM_TVENC_SYNCOFFSET_HLC(v)         BM_TVENC_SYNCOFFSET_HLC
#define BF_TVENC_SYNCOFFSET_HLC_V(e)        BF_TVENC_SYNCOFFSET_HLC(BV_TVENC_SYNCOFFSET_HLC__##e)
#define BFM_TVENC_SYNCOFFSET_HLC_V(v)       BM_TVENC_SYNCOFFSET_HLC

#define HW_TVENC_HTIMINGSYNC0                   HW(TVENC_HTIMINGSYNC0)
#define HWA_TVENC_HTIMINGSYNC0                  (0x80038000 + 0x40)
#define HWT_TVENC_HTIMINGSYNC0                  HWIO_32_RW
#define HWN_TVENC_HTIMINGSYNC0                  TVENC_HTIMINGSYNC0
#define HWI_TVENC_HTIMINGSYNC0                  
#define HW_TVENC_HTIMINGSYNC0_SET               HW(TVENC_HTIMINGSYNC0_SET)
#define HWA_TVENC_HTIMINGSYNC0_SET              (HWA_TVENC_HTIMINGSYNC0 + 0x4)
#define HWT_TVENC_HTIMINGSYNC0_SET              HWIO_32_WO
#define HWN_TVENC_HTIMINGSYNC0_SET              TVENC_HTIMINGSYNC0
#define HWI_TVENC_HTIMINGSYNC0_SET              
#define HW_TVENC_HTIMINGSYNC0_CLR               HW(TVENC_HTIMINGSYNC0_CLR)
#define HWA_TVENC_HTIMINGSYNC0_CLR              (HWA_TVENC_HTIMINGSYNC0 + 0x8)
#define HWT_TVENC_HTIMINGSYNC0_CLR              HWIO_32_WO
#define HWN_TVENC_HTIMINGSYNC0_CLR              TVENC_HTIMINGSYNC0
#define HWI_TVENC_HTIMINGSYNC0_CLR              
#define HW_TVENC_HTIMINGSYNC0_TOG               HW(TVENC_HTIMINGSYNC0_TOG)
#define HWA_TVENC_HTIMINGSYNC0_TOG              (HWA_TVENC_HTIMINGSYNC0 + 0xc)
#define HWT_TVENC_HTIMINGSYNC0_TOG              HWIO_32_WO
#define HWN_TVENC_HTIMINGSYNC0_TOG              TVENC_HTIMINGSYNC0
#define HWI_TVENC_HTIMINGSYNC0_TOG              
#define BP_TVENC_HTIMINGSYNC0_RSRVD2            26
#define BM_TVENC_HTIMINGSYNC0_RSRVD2            0xfc000000
#define BF_TVENC_HTIMINGSYNC0_RSRVD2(v)         (((v) & 0x3f) << 26)
#define BFM_TVENC_HTIMINGSYNC0_RSRVD2(v)        BM_TVENC_HTIMINGSYNC0_RSRVD2
#define BF_TVENC_HTIMINGSYNC0_RSRVD2_V(e)       BF_TVENC_HTIMINGSYNC0_RSRVD2(BV_TVENC_HTIMINGSYNC0_RSRVD2__##e)
#define BFM_TVENC_HTIMINGSYNC0_RSRVD2_V(v)      BM_TVENC_HTIMINGSYNC0_RSRVD2
#define BP_TVENC_HTIMINGSYNC0_SYNC_END          16
#define BM_TVENC_HTIMINGSYNC0_SYNC_END          0x3ff0000
#define BF_TVENC_HTIMINGSYNC0_SYNC_END(v)       (((v) & 0x3ff) << 16)
#define BFM_TVENC_HTIMINGSYNC0_SYNC_END(v)      BM_TVENC_HTIMINGSYNC0_SYNC_END
#define BF_TVENC_HTIMINGSYNC0_SYNC_END_V(e)     BF_TVENC_HTIMINGSYNC0_SYNC_END(BV_TVENC_HTIMINGSYNC0_SYNC_END__##e)
#define BFM_TVENC_HTIMINGSYNC0_SYNC_END_V(v)    BM_TVENC_HTIMINGSYNC0_SYNC_END
#define BP_TVENC_HTIMINGSYNC0_RSRVD1            10
#define BM_TVENC_HTIMINGSYNC0_RSRVD1            0xfc00
#define BF_TVENC_HTIMINGSYNC0_RSRVD1(v)         (((v) & 0x3f) << 10)
#define BFM_TVENC_HTIMINGSYNC0_RSRVD1(v)        BM_TVENC_HTIMINGSYNC0_RSRVD1
#define BF_TVENC_HTIMINGSYNC0_RSRVD1_V(e)       BF_TVENC_HTIMINGSYNC0_RSRVD1(BV_TVENC_HTIMINGSYNC0_RSRVD1__##e)
#define BFM_TVENC_HTIMINGSYNC0_RSRVD1_V(v)      BM_TVENC_HTIMINGSYNC0_RSRVD1
#define BP_TVENC_HTIMINGSYNC0_SYNC_STRT         0
#define BM_TVENC_HTIMINGSYNC0_SYNC_STRT         0x3ff
#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v)      (((v) & 0x3ff) << 0)
#define BFM_TVENC_HTIMINGSYNC0_SYNC_STRT(v)     BM_TVENC_HTIMINGSYNC0_SYNC_STRT
#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT_V(e)    BF_TVENC_HTIMINGSYNC0_SYNC_STRT(BV_TVENC_HTIMINGSYNC0_SYNC_STRT__##e)
#define BFM_TVENC_HTIMINGSYNC0_SYNC_STRT_V(v)   BM_TVENC_HTIMINGSYNC0_SYNC_STRT

#define HW_TVENC_HTIMINGSYNC1                   HW(TVENC_HTIMINGSYNC1)
#define HWA_TVENC_HTIMINGSYNC1                  (0x80038000 + 0x50)
#define HWT_TVENC_HTIMINGSYNC1                  HWIO_32_RW
#define HWN_TVENC_HTIMINGSYNC1                  TVENC_HTIMINGSYNC1
#define HWI_TVENC_HTIMINGSYNC1                  
#define HW_TVENC_HTIMINGSYNC1_SET               HW(TVENC_HTIMINGSYNC1_SET)
#define HWA_TVENC_HTIMINGSYNC1_SET              (HWA_TVENC_HTIMINGSYNC1 + 0x4)
#define HWT_TVENC_HTIMINGSYNC1_SET              HWIO_32_WO
#define HWN_TVENC_HTIMINGSYNC1_SET              TVENC_HTIMINGSYNC1
#define HWI_TVENC_HTIMINGSYNC1_SET              
#define HW_TVENC_HTIMINGSYNC1_CLR               HW(TVENC_HTIMINGSYNC1_CLR)
#define HWA_TVENC_HTIMINGSYNC1_CLR              (HWA_TVENC_HTIMINGSYNC1 + 0x8)
#define HWT_TVENC_HTIMINGSYNC1_CLR              HWIO_32_WO
#define HWN_TVENC_HTIMINGSYNC1_CLR              TVENC_HTIMINGSYNC1
#define HWI_TVENC_HTIMINGSYNC1_CLR              
#define HW_TVENC_HTIMINGSYNC1_TOG               HW(TVENC_HTIMINGSYNC1_TOG)
#define HWA_TVENC_HTIMINGSYNC1_TOG              (HWA_TVENC_HTIMINGSYNC1 + 0xc)
#define HWT_TVENC_HTIMINGSYNC1_TOG              HWIO_32_WO
#define HWN_TVENC_HTIMINGSYNC1_TOG              TVENC_HTIMINGSYNC1
#define HWI_TVENC_HTIMINGSYNC1_TOG              
#define BP_TVENC_HTIMINGSYNC1_RSRVD2            26
#define BM_TVENC_HTIMINGSYNC1_RSRVD2            0xfc000000
#define BF_TVENC_HTIMINGSYNC1_RSRVD2(v)         (((v) & 0x3f) << 26)
#define BFM_TVENC_HTIMINGSYNC1_RSRVD2(v)        BM_TVENC_HTIMINGSYNC1_RSRVD2
#define BF_TVENC_HTIMINGSYNC1_RSRVD2_V(e)       BF_TVENC_HTIMINGSYNC1_RSRVD2(BV_TVENC_HTIMINGSYNC1_RSRVD2__##e)
#define BFM_TVENC_HTIMINGSYNC1_RSRVD2_V(v)      BM_TVENC_HTIMINGSYNC1_RSRVD2
#define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND        16
#define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND        0x3ff0000
#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v)     (((v) & 0x3ff) << 16)
#define BFM_TVENC_HTIMINGSYNC1_SYNC_EQEND(v)    BM_TVENC_HTIMINGSYNC1_SYNC_EQEND
#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND_V(e)   BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(BV_TVENC_HTIMINGSYNC1_SYNC_EQEND__##e)
#define BFM_TVENC_HTIMINGSYNC1_SYNC_EQEND_V(v)  BM_TVENC_HTIMINGSYNC1_SYNC_EQEND
#define BP_TVENC_HTIMINGSYNC1_RSRVD1            10
#define BM_TVENC_HTIMINGSYNC1_RSRVD1            0xfc00
#define BF_TVENC_HTIMINGSYNC1_RSRVD1(v)         (((v) & 0x3f) << 10)
#define BFM_TVENC_HTIMINGSYNC1_RSRVD1(v)        BM_TVENC_HTIMINGSYNC1_RSRVD1
#define BF_TVENC_HTIMINGSYNC1_RSRVD1_V(e)       BF_TVENC_HTIMINGSYNC1_RSRVD1(BV_TVENC_HTIMINGSYNC1_RSRVD1__##e)
#define BFM_TVENC_HTIMINGSYNC1_RSRVD1_V(v)      BM_TVENC_HTIMINGSYNC1_RSRVD1
#define BP_TVENC_HTIMINGSYNC1_SYNC_SREND        0
#define BM_TVENC_HTIMINGSYNC1_SYNC_SREND        0x3ff
#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v)     (((v) & 0x3ff) << 0)
#define BFM_TVENC_HTIMINGSYNC1_SYNC_SREND(v)    BM_TVENC_HTIMINGSYNC1_SYNC_SREND
#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND_V(e)   BF_TVENC_HTIMINGSYNC1_SYNC_SREND(BV_TVENC_HTIMINGSYNC1_SYNC_SREND__##e)
#define BFM_TVENC_HTIMINGSYNC1_SYNC_SREND_V(v)  BM_TVENC_HTIMINGSYNC1_SYNC_SREND

#define HW_TVENC_HTIMINGACTIVE                  HW(TVENC_HTIMINGACTIVE)
#define HWA_TVENC_HTIMINGACTIVE                 (0x80038000 + 0x60)
#define HWT_TVENC_HTIMINGACTIVE                 HWIO_32_RW
#define HWN_TVENC_HTIMINGACTIVE                 TVENC_HTIMINGACTIVE
#define HWI_TVENC_HTIMINGACTIVE                 
#define HW_TVENC_HTIMINGACTIVE_SET              HW(TVENC_HTIMINGACTIVE_SET)
#define HWA_TVENC_HTIMINGACTIVE_SET             (HWA_TVENC_HTIMINGACTIVE + 0x4)
#define HWT_TVENC_HTIMINGACTIVE_SET             HWIO_32_WO
#define HWN_TVENC_HTIMINGACTIVE_SET             TVENC_HTIMINGACTIVE
#define HWI_TVENC_HTIMINGACTIVE_SET             
#define HW_TVENC_HTIMINGACTIVE_CLR              HW(TVENC_HTIMINGACTIVE_CLR)
#define HWA_TVENC_HTIMINGACTIVE_CLR             (HWA_TVENC_HTIMINGACTIVE + 0x8)
#define HWT_TVENC_HTIMINGACTIVE_CLR             HWIO_32_WO
#define HWN_TVENC_HTIMINGACTIVE_CLR             TVENC_HTIMINGACTIVE
#define HWI_TVENC_HTIMINGACTIVE_CLR             
#define HW_TVENC_HTIMINGACTIVE_TOG              HW(TVENC_HTIMINGACTIVE_TOG)
#define HWA_TVENC_HTIMINGACTIVE_TOG             (HWA_TVENC_HTIMINGACTIVE + 0xc)
#define HWT_TVENC_HTIMINGACTIVE_TOG             HWIO_32_WO
#define HWN_TVENC_HTIMINGACTIVE_TOG             TVENC_HTIMINGACTIVE
#define HWI_TVENC_HTIMINGACTIVE_TOG             
#define BP_TVENC_HTIMINGACTIVE_RSRVD2           26
#define BM_TVENC_HTIMINGACTIVE_RSRVD2           0xfc000000
#define BF_TVENC_HTIMINGACTIVE_RSRVD2(v)        (((v) & 0x3f) << 26)
#define BFM_TVENC_HTIMINGACTIVE_RSRVD2(v)       BM_TVENC_HTIMINGACTIVE_RSRVD2
#define BF_TVENC_HTIMINGACTIVE_RSRVD2_V(e)      BF_TVENC_HTIMINGACTIVE_RSRVD2(BV_TVENC_HTIMINGACTIVE_RSRVD2__##e)
#define BFM_TVENC_HTIMINGACTIVE_RSRVD2_V(v)     BM_TVENC_HTIMINGACTIVE_RSRVD2
#define BP_TVENC_HTIMINGACTIVE_ACTV_END         16
#define BM_TVENC_HTIMINGACTIVE_ACTV_END         0x3ff0000
#define BF_TVENC_HTIMINGACTIVE_ACTV_END(v)      (((v) & 0x3ff) << 16)
#define BFM_TVENC_HTIMINGACTIVE_ACTV_END(v)     BM_TVENC_HTIMINGACTIVE_ACTV_END
#define BF_TVENC_HTIMINGACTIVE_ACTV_END_V(e)    BF_TVENC_HTIMINGACTIVE_ACTV_END(BV_TVENC_HTIMINGACTIVE_ACTV_END__##e)
#define BFM_TVENC_HTIMINGACTIVE_ACTV_END_V(v)   BM_TVENC_HTIMINGACTIVE_ACTV_END
#define BP_TVENC_HTIMINGACTIVE_RSRVD1           10
#define BM_TVENC_HTIMINGACTIVE_RSRVD1           0xfc00
#define BF_TVENC_HTIMINGACTIVE_RSRVD1(v)        (((v) & 0x3f) << 10)
#define BFM_TVENC_HTIMINGACTIVE_RSRVD1(v)       BM_TVENC_HTIMINGACTIVE_RSRVD1
#define BF_TVENC_HTIMINGACTIVE_RSRVD1_V(e)      BF_TVENC_HTIMINGACTIVE_RSRVD1(BV_TVENC_HTIMINGACTIVE_RSRVD1__##e)
#define BFM_TVENC_HTIMINGACTIVE_RSRVD1_V(v)     BM_TVENC_HTIMINGACTIVE_RSRVD1
#define BP_TVENC_HTIMINGACTIVE_ACTV_STRT        0
#define BM_TVENC_HTIMINGACTIVE_ACTV_STRT        0x3ff
#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v)     (((v) & 0x3ff) << 0)
#define BFM_TVENC_HTIMINGACTIVE_ACTV_STRT(v)    BM_TVENC_HTIMINGACTIVE_ACTV_STRT
#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT_V(e)   BF_TVENC_HTIMINGACTIVE_ACTV_STRT(BV_TVENC_HTIMINGACTIVE_ACTV_STRT__##e)
#define BFM_TVENC_HTIMINGACTIVE_ACTV_STRT_V(v)  BM_TVENC_HTIMINGACTIVE_ACTV_STRT

#define HW_TVENC_HTIMINGBURST0                  HW(TVENC_HTIMINGBURST0)
#define HWA_TVENC_HTIMINGBURST0                 (0x80038000 + 0x70)
#define HWT_TVENC_HTIMINGBURST0                 HWIO_32_RW
#define HWN_TVENC_HTIMINGBURST0                 TVENC_HTIMINGBURST0
#define HWI_TVENC_HTIMINGBURST0                 
#define HW_TVENC_HTIMINGBURST0_SET              HW(TVENC_HTIMINGBURST0_SET)
#define HWA_TVENC_HTIMINGBURST0_SET             (HWA_TVENC_HTIMINGBURST0 + 0x4)
#define HWT_TVENC_HTIMINGBURST0_SET             HWIO_32_WO
#define HWN_TVENC_HTIMINGBURST0_SET             TVENC_HTIMINGBURST0
#define HWI_TVENC_HTIMINGBURST0_SET             
#define HW_TVENC_HTIMINGBURST0_CLR              HW(TVENC_HTIMINGBURST0_CLR)
#define HWA_TVENC_HTIMINGBURST0_CLR             (HWA_TVENC_HTIMINGBURST0 + 0x8)
#define HWT_TVENC_HTIMINGBURST0_CLR             HWIO_32_WO
#define HWN_TVENC_HTIMINGBURST0_CLR             TVENC_HTIMINGBURST0
#define HWI_TVENC_HTIMINGBURST0_CLR             
#define HW_TVENC_HTIMINGBURST0_TOG              HW(TVENC_HTIMINGBURST0_TOG)
#define HWA_TVENC_HTIMINGBURST0_TOG             (HWA_TVENC_HTIMINGBURST0 + 0xc)
#define HWT_TVENC_HTIMINGBURST0_TOG             HWIO_32_WO
#define HWN_TVENC_HTIMINGBURST0_TOG             TVENC_HTIMINGBURST0
#define HWI_TVENC_HTIMINGBURST0_TOG             
#define BP_TVENC_HTIMINGBURST0_RSRVD2           26
#define BM_TVENC_HTIMINGBURST0_RSRVD2           0xfc000000
#define BF_TVENC_HTIMINGBURST0_RSRVD2(v)        (((v) & 0x3f) << 26)
#define BFM_TVENC_HTIMINGBURST0_RSRVD2(v)       BM_TVENC_HTIMINGBURST0_RSRVD2
#define BF_TVENC_HTIMINGBURST0_RSRVD2_V(e)      BF_TVENC_HTIMINGBURST0_RSRVD2(BV_TVENC_HTIMINGBURST0_RSRVD2__##e)
#define BFM_TVENC_HTIMINGBURST0_RSRVD2_V(v)     BM_TVENC_HTIMINGBURST0_RSRVD2
#define BP_TVENC_HTIMINGBURST0_WBRST_STRT       16
#define BM_TVENC_HTIMINGBURST0_WBRST_STRT       0x3ff0000
#define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v)    (((v) & 0x3ff) << 16)
#define BFM_TVENC_HTIMINGBURST0_WBRST_STRT(v)   BM_TVENC_HTIMINGBURST0_WBRST_STRT
#define BF_TVENC_HTIMINGBURST0_WBRST_STRT_V(e)  BF_TVENC_HTIMINGBURST0_WBRST_STRT(BV_TVENC_HTIMINGBURST0_WBRST_STRT__##e)
#define BFM_TVENC_HTIMINGBURST0_WBRST_STRT_V(v) BM_TVENC_HTIMINGBURST0_WBRST_STRT
#define BP_TVENC_HTIMINGBURST0_RSRVD1           10
#define BM_TVENC_HTIMINGBURST0_RSRVD1           0xfc00
#define BF_TVENC_HTIMINGBURST0_RSRVD1(v)        (((v) & 0x3f) << 10)
#define BFM_TVENC_HTIMINGBURST0_RSRVD1(v)       BM_TVENC_HTIMINGBURST0_RSRVD1
#define BF_TVENC_HTIMINGBURST0_RSRVD1_V(e)      BF_TVENC_HTIMINGBURST0_RSRVD1(BV_TVENC_HTIMINGBURST0_RSRVD1__##e)
#define BFM_TVENC_HTIMINGBURST0_RSRVD1_V(v)     BM_TVENC_HTIMINGBURST0_RSRVD1
#define BP_TVENC_HTIMINGBURST0_NBRST_STRT       0
#define BM_TVENC_HTIMINGBURST0_NBRST_STRT       0x3ff
#define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v)    (((v) & 0x3ff) << 0)
#define BFM_TVENC_HTIMINGBURST0_NBRST_STRT(v)   BM_TVENC_HTIMINGBURST0_NBRST_STRT
#define BF_TVENC_HTIMINGBURST0_NBRST_STRT_V(e)  BF_TVENC_HTIMINGBURST0_NBRST_STRT(BV_TVENC_HTIMINGBURST0_NBRST_STRT__##e)
#define BFM_TVENC_HTIMINGBURST0_NBRST_STRT_V(v) BM_TVENC_HTIMINGBURST0_NBRST_STRT

#define HW_TVENC_HTIMINGBURST1                  HW(TVENC_HTIMINGBURST1)
#define HWA_TVENC_HTIMINGBURST1                 (0x80038000 + 0x80)
#define HWT_TVENC_HTIMINGBURST1                 HWIO_32_RW
#define HWN_TVENC_HTIMINGBURST1                 TVENC_HTIMINGBURST1
#define HWI_TVENC_HTIMINGBURST1                 
#define HW_TVENC_HTIMINGBURST1_SET              HW(TVENC_HTIMINGBURST1_SET)
#define HWA_TVENC_HTIMINGBURST1_SET             (HWA_TVENC_HTIMINGBURST1 + 0x4)
#define HWT_TVENC_HTIMINGBURST1_SET             HWIO_32_WO
#define HWN_TVENC_HTIMINGBURST1_SET             TVENC_HTIMINGBURST1
#define HWI_TVENC_HTIMINGBURST1_SET             
#define HW_TVENC_HTIMINGBURST1_CLR              HW(TVENC_HTIMINGBURST1_CLR)
#define HWA_TVENC_HTIMINGBURST1_CLR             (HWA_TVENC_HTIMINGBURST1 + 0x8)
#define HWT_TVENC_HTIMINGBURST1_CLR             HWIO_32_WO
#define HWN_TVENC_HTIMINGBURST1_CLR             TVENC_HTIMINGBURST1
#define HWI_TVENC_HTIMINGBURST1_CLR             
#define HW_TVENC_HTIMINGBURST1_TOG              HW(TVENC_HTIMINGBURST1_TOG)
#define HWA_TVENC_HTIMINGBURST1_TOG             (HWA_TVENC_HTIMINGBURST1 + 0xc)
#define HWT_TVENC_HTIMINGBURST1_TOG             HWIO_32_WO
#define HWN_TVENC_HTIMINGBURST1_TOG             TVENC_HTIMINGBURST1
#define HWI_TVENC_HTIMINGBURST1_TOG             
#define BP_TVENC_HTIMINGBURST1_RSRVD1           10
#define BM_TVENC_HTIMINGBURST1_RSRVD1           0xfffffc00
#define BF_TVENC_HTIMINGBURST1_RSRVD1(v)        (((v) & 0x3fffff) << 10)
#define BFM_TVENC_HTIMINGBURST1_RSRVD1(v)       BM_TVENC_HTIMINGBURST1_RSRVD1
#define BF_TVENC_HTIMINGBURST1_RSRVD1_V(e)      BF_TVENC_HTIMINGBURST1_RSRVD1(BV_TVENC_HTIMINGBURST1_RSRVD1__##e)
#define BFM_TVENC_HTIMINGBURST1_RSRVD1_V(v)     BM_TVENC_HTIMINGBURST1_RSRVD1
#define BP_TVENC_HTIMINGBURST1_BRST_END         0
#define BM_TVENC_HTIMINGBURST1_BRST_END         0x3ff
#define BF_TVENC_HTIMINGBURST1_BRST_END(v)      (((v) & 0x3ff) << 0)
#define BFM_TVENC_HTIMINGBURST1_BRST_END(v)     BM_TVENC_HTIMINGBURST1_BRST_END
#define BF_TVENC_HTIMINGBURST1_BRST_END_V(e)    BF_TVENC_HTIMINGBURST1_BRST_END(BV_TVENC_HTIMINGBURST1_BRST_END__##e)
#define BFM_TVENC_HTIMINGBURST1_BRST_END_V(v)   BM_TVENC_HTIMINGBURST1_BRST_END

#define HW_TVENC_VTIMING0                   HW(TVENC_VTIMING0)
#define HWA_TVENC_VTIMING0                  (0x80038000 + 0x90)
#define HWT_TVENC_VTIMING0                  HWIO_32_RW
#define HWN_TVENC_VTIMING0                  TVENC_VTIMING0
#define HWI_TVENC_VTIMING0                  
#define HW_TVENC_VTIMING0_SET               HW(TVENC_VTIMING0_SET)
#define HWA_TVENC_VTIMING0_SET              (HWA_TVENC_VTIMING0 + 0x4)
#define HWT_TVENC_VTIMING0_SET              HWIO_32_WO
#define HWN_TVENC_VTIMING0_SET              TVENC_VTIMING0
#define HWI_TVENC_VTIMING0_SET              
#define HW_TVENC_VTIMING0_CLR               HW(TVENC_VTIMING0_CLR)
#define HWA_TVENC_VTIMING0_CLR              (HWA_TVENC_VTIMING0 + 0x8)
#define HWT_TVENC_VTIMING0_CLR              HWIO_32_WO
#define HWN_TVENC_VTIMING0_CLR              TVENC_VTIMING0
#define HWI_TVENC_VTIMING0_CLR              
#define HW_TVENC_VTIMING0_TOG               HW(TVENC_VTIMING0_TOG)
#define HWA_TVENC_VTIMING0_TOG              (HWA_TVENC_VTIMING0 + 0xc)
#define HWT_TVENC_VTIMING0_TOG              HWIO_32_WO
#define HWN_TVENC_VTIMING0_TOG              TVENC_VTIMING0
#define HWI_TVENC_VTIMING0_TOG              
#define BP_TVENC_VTIMING0_RSRVD3            26
#define BM_TVENC_VTIMING0_RSRVD3            0xfc000000
#define BF_TVENC_VTIMING0_RSRVD3(v)         (((v) & 0x3f) << 26)
#define BFM_TVENC_VTIMING0_RSRVD3(v)        BM_TVENC_VTIMING0_RSRVD3
#define BF_TVENC_VTIMING0_RSRVD3_V(e)       BF_TVENC_VTIMING0_RSRVD3(BV_TVENC_VTIMING0_RSRVD3__##e)
#define BFM_TVENC_VTIMING0_RSRVD3_V(v)      BM_TVENC_VTIMING0_RSRVD3
#define BP_TVENC_VTIMING0_VSTRT_PREEQ       16
#define BM_TVENC_VTIMING0_VSTRT_PREEQ       0x3ff0000
#define BF_TVENC_VTIMING0_VSTRT_PREEQ(v)    (((v) & 0x3ff) << 16)
#define BFM_TVENC_VTIMING0_VSTRT_PREEQ(v)   BM_TVENC_VTIMING0_VSTRT_PREEQ
#define BF_TVENC_VTIMING0_VSTRT_PREEQ_V(e)  BF_TVENC_VTIMING0_VSTRT_PREEQ(BV_TVENC_VTIMING0_VSTRT_PREEQ__##e)
#define BFM_TVENC_VTIMING0_VSTRT_PREEQ_V(v) BM_TVENC_VTIMING0_VSTRT_PREEQ
#define BP_TVENC_VTIMING0_RSRVD2            14
#define BM_TVENC_VTIMING0_RSRVD2            0xc000
#define BF_TVENC_VTIMING0_RSRVD2(v)         (((v) & 0x3) << 14)
#define BFM_TVENC_VTIMING0_RSRVD2(v)        BM_TVENC_VTIMING0_RSRVD2
#define BF_TVENC_VTIMING0_RSRVD2_V(e)       BF_TVENC_VTIMING0_RSRVD2(BV_TVENC_VTIMING0_RSRVD2__##e)
#define BFM_TVENC_VTIMING0_RSRVD2_V(v)      BM_TVENC_VTIMING0_RSRVD2
#define BP_TVENC_VTIMING0_VSTRT_ACTV        8
#define BM_TVENC_VTIMING0_VSTRT_ACTV        0x3f00
#define BF_TVENC_VTIMING0_VSTRT_ACTV(v)     (((v) & 0x3f) << 8)
#define BFM_TVENC_VTIMING0_VSTRT_ACTV(v)    BM_TVENC_VTIMING0_VSTRT_ACTV
#define BF_TVENC_VTIMING0_VSTRT_ACTV_V(e)   BF_TVENC_VTIMING0_VSTRT_ACTV(BV_TVENC_VTIMING0_VSTRT_ACTV__##e)
#define BFM_TVENC_VTIMING0_VSTRT_ACTV_V(v)  BM_TVENC_VTIMING0_VSTRT_ACTV
#define BP_TVENC_VTIMING0_RSRVD1            6
#define BM_TVENC_VTIMING0_RSRVD1            0xc0
#define BF_TVENC_VTIMING0_RSRVD1(v)         (((v) & 0x3) << 6)
#define BFM_TVENC_VTIMING0_RSRVD1(v)        BM_TVENC_VTIMING0_RSRVD1
#define BF_TVENC_VTIMING0_RSRVD1_V(e)       BF_TVENC_VTIMING0_RSRVD1(BV_TVENC_VTIMING0_RSRVD1__##e)
#define BFM_TVENC_VTIMING0_RSRVD1_V(v)      BM_TVENC_VTIMING0_RSRVD1
#define BP_TVENC_VTIMING0_VSTRT_SUBPH       0
#define BM_TVENC_VTIMING0_VSTRT_SUBPH       0x3f
#define BF_TVENC_VTIMING0_VSTRT_SUBPH(v)    (((v) & 0x3f) << 0)
#define BFM_TVENC_VTIMING0_VSTRT_SUBPH(v)   BM_TVENC_VTIMING0_VSTRT_SUBPH
#define BF_TVENC_VTIMING0_VSTRT_SUBPH_V(e)  BF_TVENC_VTIMING0_VSTRT_SUBPH(BV_TVENC_VTIMING0_VSTRT_SUBPH__##e)
#define BFM_TVENC_VTIMING0_VSTRT_SUBPH_V(v) BM_TVENC_VTIMING0_VSTRT_SUBPH

#define HW_TVENC_VTIMING1                       HW(TVENC_VTIMING1)
#define HWA_TVENC_VTIMING1                      (0x80038000 + 0xa0)
#define HWT_TVENC_VTIMING1                      HWIO_32_RW
#define HWN_TVENC_VTIMING1                      TVENC_VTIMING1
#define HWI_TVENC_VTIMING1                      
#define HW_TVENC_VTIMING1_SET                   HW(TVENC_VTIMING1_SET)
#define HWA_TVENC_VTIMING1_SET                  (HWA_TVENC_VTIMING1 + 0x4)
#define HWT_TVENC_VTIMING1_SET                  HWIO_32_WO
#define HWN_TVENC_VTIMING1_SET                  TVENC_VTIMING1
#define HWI_TVENC_VTIMING1_SET                  
#define HW_TVENC_VTIMING1_CLR                   HW(TVENC_VTIMING1_CLR)
#define HWA_TVENC_VTIMING1_CLR                  (HWA_TVENC_VTIMING1 + 0x8)
#define HWT_TVENC_VTIMING1_CLR                  HWIO_32_WO
#define HWN_TVENC_VTIMING1_CLR                  TVENC_VTIMING1
#define HWI_TVENC_VTIMING1_CLR                  
#define HW_TVENC_VTIMING1_TOG                   HW(TVENC_VTIMING1_TOG)
#define HWA_TVENC_VTIMING1_TOG                  (HWA_TVENC_VTIMING1 + 0xc)
#define HWT_TVENC_VTIMING1_TOG                  HWIO_32_WO
#define HWN_TVENC_VTIMING1_TOG                  TVENC_VTIMING1
#define HWI_TVENC_VTIMING1_TOG                  
#define BP_TVENC_VTIMING1_RSRVD3                30
#define BM_TVENC_VTIMING1_RSRVD3                0xc0000000
#define BF_TVENC_VTIMING1_RSRVD3(v)             (((v) & 0x3) << 30)
#define BFM_TVENC_VTIMING1_RSRVD3(v)            BM_TVENC_VTIMING1_RSRVD3
#define BF_TVENC_VTIMING1_RSRVD3_V(e)           BF_TVENC_VTIMING1_RSRVD3(BV_TVENC_VTIMING1_RSRVD3__##e)
#define BFM_TVENC_VTIMING1_RSRVD3_V(v)          BM_TVENC_VTIMING1_RSRVD3
#define BP_TVENC_VTIMING1_VSTRT_POSTEQ          24
#define BM_TVENC_VTIMING1_VSTRT_POSTEQ          0x3f000000
#define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v)       (((v) & 0x3f) << 24)
#define BFM_TVENC_VTIMING1_VSTRT_POSTEQ(v)      BM_TVENC_VTIMING1_VSTRT_POSTEQ
#define BF_TVENC_VTIMING1_VSTRT_POSTEQ_V(e)     BF_TVENC_VTIMING1_VSTRT_POSTEQ(BV_TVENC_VTIMING1_VSTRT_POSTEQ__##e)
#define BFM_TVENC_VTIMING1_VSTRT_POSTEQ_V(v)    BM_TVENC_VTIMING1_VSTRT_POSTEQ
#define BP_TVENC_VTIMING1_RSRVD2                22
#define BM_TVENC_VTIMING1_RSRVD2                0xc00000
#define BF_TVENC_VTIMING1_RSRVD2(v)             (((v) & 0x3) << 22)
#define BFM_TVENC_VTIMING1_RSRVD2(v)            BM_TVENC_VTIMING1_RSRVD2
#define BF_TVENC_VTIMING1_RSRVD2_V(e)           BF_TVENC_VTIMING1_RSRVD2(BV_TVENC_VTIMING1_RSRVD2__##e)
#define BFM_TVENC_VTIMING1_RSRVD2_V(v)          BM_TVENC_VTIMING1_RSRVD2
#define BP_TVENC_VTIMING1_VSTRT_SERRA           16
#define BM_TVENC_VTIMING1_VSTRT_SERRA           0x3f0000
#define BF_TVENC_VTIMING1_VSTRT_SERRA(v)        (((v) & 0x3f) << 16)
#define BFM_TVENC_VTIMING1_VSTRT_SERRA(v)       BM_TVENC_VTIMING1_VSTRT_SERRA
#define BF_TVENC_VTIMING1_VSTRT_SERRA_V(e)      BF_TVENC_VTIMING1_VSTRT_SERRA(BV_TVENC_VTIMING1_VSTRT_SERRA__##e)
#define BFM_TVENC_VTIMING1_VSTRT_SERRA_V(v)     BM_TVENC_VTIMING1_VSTRT_SERRA
#define BP_TVENC_VTIMING1_RSRVD1                10
#define BM_TVENC_VTIMING1_RSRVD1                0xfc00
#define BF_TVENC_VTIMING1_RSRVD1(v)             (((v) & 0x3f) << 10)
#define BFM_TVENC_VTIMING1_RSRVD1(v)            BM_TVENC_VTIMING1_RSRVD1
#define BF_TVENC_VTIMING1_RSRVD1_V(e)           BF_TVENC_VTIMING1_RSRVD1(BV_TVENC_VTIMING1_RSRVD1__##e)
#define BFM_TVENC_VTIMING1_RSRVD1_V(v)          BM_TVENC_VTIMING1_RSRVD1
#define BP_TVENC_VTIMING1_LAST_FLD_LN           0
#define BM_TVENC_VTIMING1_LAST_FLD_LN           0x3ff
#define BF_TVENC_VTIMING1_LAST_FLD_LN(v)        (((v) & 0x3ff) << 0)
#define BFM_TVENC_VTIMING1_LAST_FLD_LN(v)       BM_TVENC_VTIMING1_LAST_FLD_LN
#define BF_TVENC_VTIMING1_LAST_FLD_LN_V(e)      BF_TVENC_VTIMING1_LAST_FLD_LN(BV_TVENC_VTIMING1_LAST_FLD_LN__##e)
#define BFM_TVENC_VTIMING1_LAST_FLD_LN_V(v)     BM_TVENC_VTIMING1_LAST_FLD_LN

#define HW_TVENC_MISC                           HW(TVENC_MISC)
#define HWA_TVENC_MISC                          (0x80038000 + 0xb0)
#define HWT_TVENC_MISC                          HWIO_32_RW
#define HWN_TVENC_MISC                          TVENC_MISC
#define HWI_TVENC_MISC                          
#define HW_TVENC_MISC_SET                       HW(TVENC_MISC_SET)
#define HWA_TVENC_MISC_SET                      (HWA_TVENC_MISC + 0x4)
#define HWT_TVENC_MISC_SET                      HWIO_32_WO
#define HWN_TVENC_MISC_SET                      TVENC_MISC
#define HWI_TVENC_MISC_SET                      
#define HW_TVENC_MISC_CLR                       HW(TVENC_MISC_CLR)
#define HWA_TVENC_MISC_CLR                      (HWA_TVENC_MISC + 0x8)
#define HWT_TVENC_MISC_CLR                      HWIO_32_WO
#define HWN_TVENC_MISC_CLR                      TVENC_MISC
#define HWI_TVENC_MISC_CLR                      
#define HW_TVENC_MISC_TOG                       HW(TVENC_MISC_TOG)
#define HWA_TVENC_MISC_TOG                      (HWA_TVENC_MISC + 0xc)
#define HWT_TVENC_MISC_TOG                      HWIO_32_WO
#define HWN_TVENC_MISC_TOG                      TVENC_MISC
#define HWI_TVENC_MISC_TOG                      
#define BP_TVENC_MISC_RSRVD3                    25
#define BM_TVENC_MISC_RSRVD3                    0xfe000000
#define BF_TVENC_MISC_RSRVD3(v)                 (((v) & 0x7f) << 25)
#define BFM_TVENC_MISC_RSRVD3(v)                BM_TVENC_MISC_RSRVD3
#define BF_TVENC_MISC_RSRVD3_V(e)               BF_TVENC_MISC_RSRVD3(BV_TVENC_MISC_RSRVD3__##e)
#define BFM_TVENC_MISC_RSRVD3_V(v)              BM_TVENC_MISC_RSRVD3
#define BP_TVENC_MISC_LPF_RST_OFF               16
#define BM_TVENC_MISC_LPF_RST_OFF               0x1ff0000
#define BF_TVENC_MISC_LPF_RST_OFF(v)            (((v) & 0x1ff) << 16)
#define BFM_TVENC_MISC_LPF_RST_OFF(v)           BM_TVENC_MISC_LPF_RST_OFF
#define BF_TVENC_MISC_LPF_RST_OFF_V(e)          BF_TVENC_MISC_LPF_RST_OFF(BV_TVENC_MISC_LPF_RST_OFF__##e)
#define BFM_TVENC_MISC_LPF_RST_OFF_V(v)         BM_TVENC_MISC_LPF_RST_OFF
#define BP_TVENC_MISC_RSRVD2                    12
#define BM_TVENC_MISC_RSRVD2                    0xf000
#define BF_TVENC_MISC_RSRVD2(v)                 (((v) & 0xf) << 12)
#define BFM_TVENC_MISC_RSRVD2(v)                BM_TVENC_MISC_RSRVD2
#define BF_TVENC_MISC_RSRVD2_V(e)               BF_TVENC_MISC_RSRVD2(BV_TVENC_MISC_RSRVD2__##e)
#define BFM_TVENC_MISC_RSRVD2_V(v)              BM_TVENC_MISC_RSRVD2
#define BP_TVENC_MISC_NTSC_LN_CNT               11
#define BM_TVENC_MISC_NTSC_LN_CNT               0x800
#define BF_TVENC_MISC_NTSC_LN_CNT(v)            (((v) & 0x1) << 11)
#define BFM_TVENC_MISC_NTSC_LN_CNT(v)           BM_TVENC_MISC_NTSC_LN_CNT
#define BF_TVENC_MISC_NTSC_LN_CNT_V(e)          BF_TVENC_MISC_NTSC_LN_CNT(BV_TVENC_MISC_NTSC_LN_CNT__##e)
#define BFM_TVENC_MISC_NTSC_LN_CNT_V(v)         BM_TVENC_MISC_NTSC_LN_CNT
#define BP_TVENC_MISC_PAL_FSC_PHASE_ALT         10
#define BM_TVENC_MISC_PAL_FSC_PHASE_ALT         0x400
#define BF_TVENC_MISC_PAL_FSC_PHASE_ALT(v)      (((v) & 0x1) << 10)
#define BFM_TVENC_MISC_PAL_FSC_PHASE_ALT(v)     BM_TVENC_MISC_PAL_FSC_PHASE_ALT
#define BF_TVENC_MISC_PAL_FSC_PHASE_ALT_V(e)    BF_TVENC_MISC_PAL_FSC_PHASE_ALT(BV_TVENC_MISC_PAL_FSC_PHASE_ALT__##e)
#define BFM_TVENC_MISC_PAL_FSC_PHASE_ALT_V(v)   BM_TVENC_MISC_PAL_FSC_PHASE_ALT
#define BP_TVENC_MISC_FSC_PHASE_RST             8
#define BM_TVENC_MISC_FSC_PHASE_RST             0x300
#define BF_TVENC_MISC_FSC_PHASE_RST(v)          (((v) & 0x3) << 8)
#define BFM_TVENC_MISC_FSC_PHASE_RST(v)         BM_TVENC_MISC_FSC_PHASE_RST
#define BF_TVENC_MISC_FSC_PHASE_RST_V(e)        BF_TVENC_MISC_FSC_PHASE_RST(BV_TVENC_MISC_FSC_PHASE_RST__##e)
#define BFM_TVENC_MISC_FSC_PHASE_RST_V(v)       BM_TVENC_MISC_FSC_PHASE_RST
#define BP_TVENC_MISC_BRUCHB                    6
#define BM_TVENC_MISC_BRUCHB                    0xc0
#define BF_TVENC_MISC_BRUCHB(v)                 (((v) & 0x3) << 6)
#define BFM_TVENC_MISC_BRUCHB(v)                BM_TVENC_MISC_BRUCHB
#define BF_TVENC_MISC_BRUCHB_V(e)               BF_TVENC_MISC_BRUCHB(BV_TVENC_MISC_BRUCHB__##e)
#define BFM_TVENC_MISC_BRUCHB_V(v)              BM_TVENC_MISC_BRUCHB
#define BP_TVENC_MISC_AGC_LVL_CTRL              4
#define BM_TVENC_MISC_AGC_LVL_CTRL              0x30
#define BF_TVENC_MISC_AGC_LVL_CTRL(v)           (((v) & 0x3) << 4)
#define BFM_TVENC_MISC_AGC_LVL_CTRL(v)          BM_TVENC_MISC_AGC_LVL_CTRL
#define BF_TVENC_MISC_AGC_LVL_CTRL_V(e)         BF_TVENC_MISC_AGC_LVL_CTRL(BV_TVENC_MISC_AGC_LVL_CTRL__##e)
#define BFM_TVENC_MISC_AGC_LVL_CTRL_V(v)        BM_TVENC_MISC_AGC_LVL_CTRL
#define BP_TVENC_MISC_RSRVD1                    3
#define BM_TVENC_MISC_RSRVD1                    0x8
#define BF_TVENC_MISC_RSRVD1(v)                 (((v) & 0x1) << 3)
#define BFM_TVENC_MISC_RSRVD1(v)                BM_TVENC_MISC_RSRVD1
#define BF_TVENC_MISC_RSRVD1_V(e)               BF_TVENC_MISC_RSRVD1(BV_TVENC_MISC_RSRVD1__##e)
#define BFM_TVENC_MISC_RSRVD1_V(v)              BM_TVENC_MISC_RSRVD1
#define BP_TVENC_MISC_CS_INVERT_CTRL            2
#define BM_TVENC_MISC_CS_INVERT_CTRL            0x4
#define BF_TVENC_MISC_CS_INVERT_CTRL(v)         (((v) & 0x1) << 2)
#define BFM_TVENC_MISC_CS_INVERT_CTRL(v)        BM_TVENC_MISC_CS_INVERT_CTRL
#define BF_TVENC_MISC_CS_INVERT_CTRL_V(e)       BF_TVENC_MISC_CS_INVERT_CTRL(BV_TVENC_MISC_CS_INVERT_CTRL__##e)
#define BFM_TVENC_MISC_CS_INVERT_CTRL_V(v)      BM_TVENC_MISC_CS_INVERT_CTRL
#define BP_TVENC_MISC_Y_BLANK_CTRL              0
#define BM_TVENC_MISC_Y_BLANK_CTRL              0x3
#define BF_TVENC_MISC_Y_BLANK_CTRL(v)           (((v) & 0x3) << 0)
#define BFM_TVENC_MISC_Y_BLANK_CTRL(v)          BM_TVENC_MISC_Y_BLANK_CTRL
#define BF_TVENC_MISC_Y_BLANK_CTRL_V(e)         BF_TVENC_MISC_Y_BLANK_CTRL(BV_TVENC_MISC_Y_BLANK_CTRL__##e)
#define BFM_TVENC_MISC_Y_BLANK_CTRL_V(v)        BM_TVENC_MISC_Y_BLANK_CTRL

#define HW_TVENC_COLORSUB0                  HW(TVENC_COLORSUB0)
#define HWA_TVENC_COLORSUB0                 (0x80038000 + 0xc0)
#define HWT_TVENC_COLORSUB0                 HWIO_32_RW
#define HWN_TVENC_COLORSUB0                 TVENC_COLORSUB0
#define HWI_TVENC_COLORSUB0                 
#define HW_TVENC_COLORSUB0_SET              HW(TVENC_COLORSUB0_SET)
#define HWA_TVENC_COLORSUB0_SET             (HWA_TVENC_COLORSUB0 + 0x4)
#define HWT_TVENC_COLORSUB0_SET             HWIO_32_WO
#define HWN_TVENC_COLORSUB0_SET             TVENC_COLORSUB0
#define HWI_TVENC_COLORSUB0_SET             
#define HW_TVENC_COLORSUB0_CLR              HW(TVENC_COLORSUB0_CLR)
#define HWA_TVENC_COLORSUB0_CLR             (HWA_TVENC_COLORSUB0 + 0x8)
#define HWT_TVENC_COLORSUB0_CLR             HWIO_32_WO
#define HWN_TVENC_COLORSUB0_CLR             TVENC_COLORSUB0
#define HWI_TVENC_COLORSUB0_CLR             
#define HW_TVENC_COLORSUB0_TOG              HW(TVENC_COLORSUB0_TOG)
#define HWA_TVENC_COLORSUB0_TOG             (HWA_TVENC_COLORSUB0 + 0xc)
#define HWT_TVENC_COLORSUB0_TOG             HWIO_32_WO
#define HWN_TVENC_COLORSUB0_TOG             TVENC_COLORSUB0
#define HWI_TVENC_COLORSUB0_TOG             
#define BP_TVENC_COLORSUB0_PHASE_INC        0
#define BM_TVENC_COLORSUB0_PHASE_INC        0xffffffff
#define BF_TVENC_COLORSUB0_PHASE_INC(v)     (((v) & 0xffffffff) << 0)
#define BFM_TVENC_COLORSUB0_PHASE_INC(v)    BM_TVENC_COLORSUB0_PHASE_INC
#define BF_TVENC_COLORSUB0_PHASE_INC_V(e)   BF_TVENC_COLORSUB0_PHASE_INC(BV_TVENC_COLORSUB0_PHASE_INC__##e)
#define BFM_TVENC_COLORSUB0_PHASE_INC_V(v)  BM_TVENC_COLORSUB0_PHASE_INC

#define HW_TVENC_COLORSUB1                      HW(TVENC_COLORSUB1)
#define HWA_TVENC_COLORSUB1                     (0x80038000 + 0xd0)
#define HWT_TVENC_COLORSUB1                     HWIO_32_RW
#define HWN_TVENC_COLORSUB1                     TVENC_COLORSUB1
#define HWI_TVENC_COLORSUB1                     
#define HW_TVENC_COLORSUB1_SET                  HW(TVENC_COLORSUB1_SET)
#define HWA_TVENC_COLORSUB1_SET                 (HWA_TVENC_COLORSUB1 + 0x4)
#define HWT_TVENC_COLORSUB1_SET                 HWIO_32_WO
#define HWN_TVENC_COLORSUB1_SET                 TVENC_COLORSUB1
#define HWI_TVENC_COLORSUB1_SET                 
#define HW_TVENC_COLORSUB1_CLR                  HW(TVENC_COLORSUB1_CLR)
#define HWA_TVENC_COLORSUB1_CLR                 (HWA_TVENC_COLORSUB1 + 0x8)
#define HWT_TVENC_COLORSUB1_CLR                 HWIO_32_WO
#define HWN_TVENC_COLORSUB1_CLR                 TVENC_COLORSUB1
#define HWI_TVENC_COLORSUB1_CLR                 
#define HW_TVENC_COLORSUB1_TOG                  HW(TVENC_COLORSUB1_TOG)
#define HWA_TVENC_COLORSUB1_TOG                 (HWA_TVENC_COLORSUB1 + 0xc)
#define HWT_TVENC_COLORSUB1_TOG                 HWIO_32_WO
#define HWN_TVENC_COLORSUB1_TOG                 TVENC_COLORSUB1
#define HWI_TVENC_COLORSUB1_TOG                 
#define BP_TVENC_COLORSUB1_PHASE_OFFSET         0
#define BM_TVENC_COLORSUB1_PHASE_OFFSET         0xffffffff
#define BF_TVENC_COLORSUB1_PHASE_OFFSET(v)      (((v) & 0xffffffff) << 0)
#define BFM_TVENC_COLORSUB1_PHASE_OFFSET(v)     BM_TVENC_COLORSUB1_PHASE_OFFSET
#define BF_TVENC_COLORSUB1_PHASE_OFFSET_V(e)    BF_TVENC_COLORSUB1_PHASE_OFFSET(BV_TVENC_COLORSUB1_PHASE_OFFSET__##e)
#define BFM_TVENC_COLORSUB1_PHASE_OFFSET_V(v)   BM_TVENC_COLORSUB1_PHASE_OFFSET

#define HW_TVENC_COPYPROTECT                        HW(TVENC_COPYPROTECT)
#define HWA_TVENC_COPYPROTECT                       (0x80038000 + 0xe0)
#define HWT_TVENC_COPYPROTECT                       HWIO_32_RW
#define HWN_TVENC_COPYPROTECT                       TVENC_COPYPROTECT
#define HWI_TVENC_COPYPROTECT                       
#define HW_TVENC_COPYPROTECT_SET                    HW(TVENC_COPYPROTECT_SET)
#define HWA_TVENC_COPYPROTECT_SET                   (HWA_TVENC_COPYPROTECT + 0x4)
#define HWT_TVENC_COPYPROTECT_SET                   HWIO_32_WO
#define HWN_TVENC_COPYPROTECT_SET                   TVENC_COPYPROTECT
#define HWI_TVENC_COPYPROTECT_SET                   
#define HW_TVENC_COPYPROTECT_CLR                    HW(TVENC_COPYPROTECT_CLR)
#define HWA_TVENC_COPYPROTECT_CLR                   (HWA_TVENC_COPYPROTECT + 0x8)
#define HWT_TVENC_COPYPROTECT_CLR                   HWIO_32_WO
#define HWN_TVENC_COPYPROTECT_CLR                   TVENC_COPYPROTECT
#define HWI_TVENC_COPYPROTECT_CLR                   
#define HW_TVENC_COPYPROTECT_TOG                    HW(TVENC_COPYPROTECT_TOG)
#define HWA_TVENC_COPYPROTECT_TOG                   (HWA_TVENC_COPYPROTECT + 0xc)
#define HWT_TVENC_COPYPROTECT_TOG                   HWIO_32_WO
#define HWN_TVENC_COPYPROTECT_TOG                   TVENC_COPYPROTECT
#define HWI_TVENC_COPYPROTECT_TOG                   
#define BP_TVENC_COPYPROTECT_RSRVD1                 16
#define BM_TVENC_COPYPROTECT_RSRVD1                 0xffff0000
#define BF_TVENC_COPYPROTECT_RSRVD1(v)              (((v) & 0xffff) << 16)
#define BFM_TVENC_COPYPROTECT_RSRVD1(v)             BM_TVENC_COPYPROTECT_RSRVD1
#define BF_TVENC_COPYPROTECT_RSRVD1_V(e)            BF_TVENC_COPYPROTECT_RSRVD1(BV_TVENC_COPYPROTECT_RSRVD1__##e)
#define BFM_TVENC_COPYPROTECT_RSRVD1_V(v)           BM_TVENC_COPYPROTECT_RSRVD1
#define BP_TVENC_COPYPROTECT_WSS_ENBL               15
#define BM_TVENC_COPYPROTECT_WSS_ENBL               0x8000
#define BF_TVENC_COPYPROTECT_WSS_ENBL(v)            (((v) & 0x1) << 15)
#define BFM_TVENC_COPYPROTECT_WSS_ENBL(v)           BM_TVENC_COPYPROTECT_WSS_ENBL
#define BF_TVENC_COPYPROTECT_WSS_ENBL_V(e)          BF_TVENC_COPYPROTECT_WSS_ENBL(BV_TVENC_COPYPROTECT_WSS_ENBL__##e)
#define BFM_TVENC_COPYPROTECT_WSS_ENBL_V(v)         BM_TVENC_COPYPROTECT_WSS_ENBL
#define BP_TVENC_COPYPROTECT_CGMS_ENBL              14
#define BM_TVENC_COPYPROTECT_CGMS_ENBL              0x4000
#define BF_TVENC_COPYPROTECT_CGMS_ENBL(v)           (((v) & 0x1) << 14)
#define BFM_TVENC_COPYPROTECT_CGMS_ENBL(v)          BM_TVENC_COPYPROTECT_CGMS_ENBL
#define BF_TVENC_COPYPROTECT_CGMS_ENBL_V(e)         BF_TVENC_COPYPROTECT_CGMS_ENBL(BV_TVENC_COPYPROTECT_CGMS_ENBL__##e)
#define BFM_TVENC_COPYPROTECT_CGMS_ENBL_V(v)        BM_TVENC_COPYPROTECT_CGMS_ENBL
#define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA          0
#define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA          0x3fff
#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v)       (((v) & 0x3fff) << 0)
#define BFM_TVENC_COPYPROTECT_WSS_CGMS_DATA(v)      BM_TVENC_COPYPROTECT_WSS_CGMS_DATA
#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA_V(e)     BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(BV_TVENC_COPYPROTECT_WSS_CGMS_DATA__##e)
#define BFM_TVENC_COPYPROTECT_WSS_CGMS_DATA_V(v)    BM_TVENC_COPYPROTECT_WSS_CGMS_DATA

#define HW_TVENC_CLOSEDCAPTION                  HW(TVENC_CLOSEDCAPTION)
#define HWA_TVENC_CLOSEDCAPTION                 (0x80038000 + 0xf0)
#define HWT_TVENC_CLOSEDCAPTION                 HWIO_32_RW
#define HWN_TVENC_CLOSEDCAPTION                 TVENC_CLOSEDCAPTION
#define HWI_TVENC_CLOSEDCAPTION                 
#define HW_TVENC_CLOSEDCAPTION_SET              HW(TVENC_CLOSEDCAPTION_SET)
#define HWA_TVENC_CLOSEDCAPTION_SET             (HWA_TVENC_CLOSEDCAPTION + 0x4)
#define HWT_TVENC_CLOSEDCAPTION_SET             HWIO_32_WO
#define HWN_TVENC_CLOSEDCAPTION_SET             TVENC_CLOSEDCAPTION
#define HWI_TVENC_CLOSEDCAPTION_SET             
#define HW_TVENC_CLOSEDCAPTION_CLR              HW(TVENC_CLOSEDCAPTION_CLR)
#define HWA_TVENC_CLOSEDCAPTION_CLR             (HWA_TVENC_CLOSEDCAPTION + 0x8)
#define HWT_TVENC_CLOSEDCAPTION_CLR             HWIO_32_WO
#define HWN_TVENC_CLOSEDCAPTION_CLR             TVENC_CLOSEDCAPTION
#define HWI_TVENC_CLOSEDCAPTION_CLR             
#define HW_TVENC_CLOSEDCAPTION_TOG              HW(TVENC_CLOSEDCAPTION_TOG)
#define HWA_TVENC_CLOSEDCAPTION_TOG             (HWA_TVENC_CLOSEDCAPTION + 0xc)
#define HWT_TVENC_CLOSEDCAPTION_TOG             HWIO_32_WO
#define HWN_TVENC_CLOSEDCAPTION_TOG             TVENC_CLOSEDCAPTION
#define HWI_TVENC_CLOSEDCAPTION_TOG             
#define BP_TVENC_CLOSEDCAPTION_RSRVD1           20
#define BM_TVENC_CLOSEDCAPTION_RSRVD1           0xfff00000
#define BF_TVENC_CLOSEDCAPTION_RSRVD1(v)        (((v) & 0xfff) << 20)
#define BFM_TVENC_CLOSEDCAPTION_RSRVD1(v)       BM_TVENC_CLOSEDCAPTION_RSRVD1
#define BF_TVENC_CLOSEDCAPTION_RSRVD1_V(e)      BF_TVENC_CLOSEDCAPTION_RSRVD1(BV_TVENC_CLOSEDCAPTION_RSRVD1__##e)
#define BFM_TVENC_CLOSEDCAPTION_RSRVD1_V(v)     BM_TVENC_CLOSEDCAPTION_RSRVD1
#define BP_TVENC_CLOSEDCAPTION_CC_ENBL          18
#define BM_TVENC_CLOSEDCAPTION_CC_ENBL          0xc0000
#define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v)       (((v) & 0x3) << 18)
#define BFM_TVENC_CLOSEDCAPTION_CC_ENBL(v)      BM_TVENC_CLOSEDCAPTION_CC_ENBL
#define BF_TVENC_CLOSEDCAPTION_CC_ENBL_V(e)     BF_TVENC_CLOSEDCAPTION_CC_ENBL(BV_TVENC_CLOSEDCAPTION_CC_ENBL__##e)
#define BFM_TVENC_CLOSEDCAPTION_CC_ENBL_V(v)    BM_TVENC_CLOSEDCAPTION_CC_ENBL
#define BP_TVENC_CLOSEDCAPTION_CC_FILL          16
#define BM_TVENC_CLOSEDCAPTION_CC_FILL          0x30000
#define BF_TVENC_CLOSEDCAPTION_CC_FILL(v)       (((v) & 0x3) << 16)
#define BFM_TVENC_CLOSEDCAPTION_CC_FILL(v)      BM_TVENC_CLOSEDCAPTION_CC_FILL
#define BF_TVENC_CLOSEDCAPTION_CC_FILL_V(e)     BF_TVENC_CLOSEDCAPTION_CC_FILL(BV_TVENC_CLOSEDCAPTION_CC_FILL__##e)
#define BFM_TVENC_CLOSEDCAPTION_CC_FILL_V(v)    BM_TVENC_CLOSEDCAPTION_CC_FILL
#define BP_TVENC_CLOSEDCAPTION_CC_DATA          0
#define BM_TVENC_CLOSEDCAPTION_CC_DATA          0xffff
#define BF_TVENC_CLOSEDCAPTION_CC_DATA(v)       (((v) & 0xffff) << 0)
#define BFM_TVENC_CLOSEDCAPTION_CC_DATA(v)      BM_TVENC_CLOSEDCAPTION_CC_DATA
#define BF_TVENC_CLOSEDCAPTION_CC_DATA_V(e)     BF_TVENC_CLOSEDCAPTION_CC_DATA(BV_TVENC_CLOSEDCAPTION_CC_DATA__##e)
#define BFM_TVENC_CLOSEDCAPTION_CC_DATA_V(v)    BM_TVENC_CLOSEDCAPTION_CC_DATA

#define HW_TVENC_COLORBURST                 HW(TVENC_COLORBURST)
#define HWA_TVENC_COLORBURST                (0x80038000 + 0x140)
#define HWT_TVENC_COLORBURST                HWIO_32_RW
#define HWN_TVENC_COLORBURST                TVENC_COLORBURST
#define HWI_TVENC_COLORBURST                
#define HW_TVENC_COLORBURST_SET             HW(TVENC_COLORBURST_SET)
#define HWA_TVENC_COLORBURST_SET            (HWA_TVENC_COLORBURST + 0x4)
#define HWT_TVENC_COLORBURST_SET            HWIO_32_WO
#define HWN_TVENC_COLORBURST_SET            TVENC_COLORBURST
#define HWI_TVENC_COLORBURST_SET            
#define HW_TVENC_COLORBURST_CLR             HW(TVENC_COLORBURST_CLR)
#define HWA_TVENC_COLORBURST_CLR            (HWA_TVENC_COLORBURST + 0x8)
#define HWT_TVENC_COLORBURST_CLR            HWIO_32_WO
#define HWN_TVENC_COLORBURST_CLR            TVENC_COLORBURST
#define HWI_TVENC_COLORBURST_CLR            
#define HW_TVENC_COLORBURST_TOG             HW(TVENC_COLORBURST_TOG)
#define HWA_TVENC_COLORBURST_TOG            (HWA_TVENC_COLORBURST + 0xc)
#define HWT_TVENC_COLORBURST_TOG            HWIO_32_WO
#define HWN_TVENC_COLORBURST_TOG            TVENC_COLORBURST
#define HWI_TVENC_COLORBURST_TOG            
#define BP_TVENC_COLORBURST_NBA             24
#define BM_TVENC_COLORBURST_NBA             0xff000000
#define BF_TVENC_COLORBURST_NBA(v)          (((v) & 0xff) << 24)
#define BFM_TVENC_COLORBURST_NBA(v)         BM_TVENC_COLORBURST_NBA
#define BF_TVENC_COLORBURST_NBA_V(e)        BF_TVENC_COLORBURST_NBA(BV_TVENC_COLORBURST_NBA__##e)
#define BFM_TVENC_COLORBURST_NBA_V(v)       BM_TVENC_COLORBURST_NBA
#define BP_TVENC_COLORBURST_PBA             16
#define BM_TVENC_COLORBURST_PBA             0xff0000
#define BF_TVENC_COLORBURST_PBA(v)          (((v) & 0xff) << 16)
#define BFM_TVENC_COLORBURST_PBA(v)         BM_TVENC_COLORBURST_PBA
#define BF_TVENC_COLORBURST_PBA_V(e)        BF_TVENC_COLORBURST_PBA(BV_TVENC_COLORBURST_PBA__##e)
#define BFM_TVENC_COLORBURST_PBA_V(v)       BM_TVENC_COLORBURST_PBA
#define BP_TVENC_COLORBURST_RSRVD1          12
#define BM_TVENC_COLORBURST_RSRVD1          0xf000
#define BF_TVENC_COLORBURST_RSRVD1(v)       (((v) & 0xf) << 12)
#define BFM_TVENC_COLORBURST_RSRVD1(v)      BM_TVENC_COLORBURST_RSRVD1
#define BF_TVENC_COLORBURST_RSRVD1_V(e)     BF_TVENC_COLORBURST_RSRVD1(BV_TVENC_COLORBURST_RSRVD1__##e)
#define BFM_TVENC_COLORBURST_RSRVD1_V(v)    BM_TVENC_COLORBURST_RSRVD1
#define BP_TVENC_COLORBURST_RSRVD2          0
#define BM_TVENC_COLORBURST_RSRVD2          0xfff
#define BF_TVENC_COLORBURST_RSRVD2(v)       (((v) & 0xfff) << 0)
#define BFM_TVENC_COLORBURST_RSRVD2(v)      BM_TVENC_COLORBURST_RSRVD2
#define BF_TVENC_COLORBURST_RSRVD2_V(e)     BF_TVENC_COLORBURST_RSRVD2(BV_TVENC_COLORBURST_RSRVD2__##e)
#define BFM_TVENC_COLORBURST_RSRVD2_V(v)    BM_TVENC_COLORBURST_RSRVD2

#define HW_TVENC_MACROVISION0               HW(TVENC_MACROVISION0)
#define HWA_TVENC_MACROVISION0              (0x80038000 + 0x150)
#define HWT_TVENC_MACROVISION0              HWIO_32_RW
#define HWN_TVENC_MACROVISION0              TVENC_MACROVISION0
#define HWI_TVENC_MACROVISION0              
#define HW_TVENC_MACROVISION0_SET           HW(TVENC_MACROVISION0_SET)
#define HWA_TVENC_MACROVISION0_SET          (HWA_TVENC_MACROVISION0 + 0x4)
#define HWT_TVENC_MACROVISION0_SET          HWIO_32_WO
#define HWN_TVENC_MACROVISION0_SET          TVENC_MACROVISION0
#define HWI_TVENC_MACROVISION0_SET          
#define HW_TVENC_MACROVISION0_CLR           HW(TVENC_MACROVISION0_CLR)
#define HWA_TVENC_MACROVISION0_CLR          (HWA_TVENC_MACROVISION0 + 0x8)
#define HWT_TVENC_MACROVISION0_CLR          HWIO_32_WO
#define HWN_TVENC_MACROVISION0_CLR          TVENC_MACROVISION0
#define HWI_TVENC_MACROVISION0_CLR          
#define HW_TVENC_MACROVISION0_TOG           HW(TVENC_MACROVISION0_TOG)
#define HWA_TVENC_MACROVISION0_TOG          (HWA_TVENC_MACROVISION0 + 0xc)
#define HWT_TVENC_MACROVISION0_TOG          HWIO_32_WO
#define HWN_TVENC_MACROVISION0_TOG          TVENC_MACROVISION0
#define HWI_TVENC_MACROVISION0_TOG          
#define BP_TVENC_MACROVISION0_DATA          0
#define BM_TVENC_MACROVISION0_DATA          0xffffffff
#define BF_TVENC_MACROVISION0_DATA(v)       (((v) & 0xffffffff) << 0)
#define BFM_TVENC_MACROVISION0_DATA(v)      BM_TVENC_MACROVISION0_DATA
#define BF_TVENC_MACROVISION0_DATA_V(e)     BF_TVENC_MACROVISION0_DATA(BV_TVENC_MACROVISION0_DATA__##e)
#define BFM_TVENC_MACROVISION0_DATA_V(v)    BM_TVENC_MACROVISION0_DATA

#define HW_TVENC_MACROVISION1               HW(TVENC_MACROVISION1)
#define HWA_TVENC_MACROVISION1              (0x80038000 + 0x160)
#define HWT_TVENC_MACROVISION1              HWIO_32_RW
#define HWN_TVENC_MACROVISION1              TVENC_MACROVISION1
#define HWI_TVENC_MACROVISION1              
#define HW_TVENC_MACROVISION1_SET           HW(TVENC_MACROVISION1_SET)
#define HWA_TVENC_MACROVISION1_SET          (HWA_TVENC_MACROVISION1 + 0x4)
#define HWT_TVENC_MACROVISION1_SET          HWIO_32_WO
#define HWN_TVENC_MACROVISION1_SET          TVENC_MACROVISION1
#define HWI_TVENC_MACROVISION1_SET          
#define HW_TVENC_MACROVISION1_CLR           HW(TVENC_MACROVISION1_CLR)
#define HWA_TVENC_MACROVISION1_CLR          (HWA_TVENC_MACROVISION1 + 0x8)
#define HWT_TVENC_MACROVISION1_CLR          HWIO_32_WO
#define HWN_TVENC_MACROVISION1_CLR          TVENC_MACROVISION1
#define HWI_TVENC_MACROVISION1_CLR          
#define HW_TVENC_MACROVISION1_TOG           HW(TVENC_MACROVISION1_TOG)
#define HWA_TVENC_MACROVISION1_TOG          (HWA_TVENC_MACROVISION1 + 0xc)
#define HWT_TVENC_MACROVISION1_TOG          HWIO_32_WO
#define HWN_TVENC_MACROVISION1_TOG          TVENC_MACROVISION1
#define HWI_TVENC_MACROVISION1_TOG          
#define BP_TVENC_MACROVISION1_DATA          0
#define BM_TVENC_MACROVISION1_DATA          0xffffffff
#define BF_TVENC_MACROVISION1_DATA(v)       (((v) & 0xffffffff) << 0)
#define BFM_TVENC_MACROVISION1_DATA(v)      BM_TVENC_MACROVISION1_DATA
#define BF_TVENC_MACROVISION1_DATA_V(e)     BF_TVENC_MACROVISION1_DATA(BV_TVENC_MACROVISION1_DATA__##e)
#define BFM_TVENC_MACROVISION1_DATA_V(v)    BM_TVENC_MACROVISION1_DATA

#define HW_TVENC_MACROVISION2               HW(TVENC_MACROVISION2)
#define HWA_TVENC_MACROVISION2              (0x80038000 + 0x170)
#define HWT_TVENC_MACROVISION2              HWIO_32_RW
#define HWN_TVENC_MACROVISION2              TVENC_MACROVISION2
#define HWI_TVENC_MACROVISION2              
#define HW_TVENC_MACROVISION2_SET           HW(TVENC_MACROVISION2_SET)
#define HWA_TVENC_MACROVISION2_SET          (HWA_TVENC_MACROVISION2 + 0x4)
#define HWT_TVENC_MACROVISION2_SET          HWIO_32_WO
#define HWN_TVENC_MACROVISION2_SET          TVENC_MACROVISION2
#define HWI_TVENC_MACROVISION2_SET          
#define HW_TVENC_MACROVISION2_CLR           HW(TVENC_MACROVISION2_CLR)
#define HWA_TVENC_MACROVISION2_CLR          (HWA_TVENC_MACROVISION2 + 0x8)
#define HWT_TVENC_MACROVISION2_CLR          HWIO_32_WO
#define HWN_TVENC_MACROVISION2_CLR          TVENC_MACROVISION2
#define HWI_TVENC_MACROVISION2_CLR          
#define HW_TVENC_MACROVISION2_TOG           HW(TVENC_MACROVISION2_TOG)
#define HWA_TVENC_MACROVISION2_TOG          (HWA_TVENC_MACROVISION2 + 0xc)
#define HWT_TVENC_MACROVISION2_TOG          HWIO_32_WO
#define HWN_TVENC_MACROVISION2_TOG          TVENC_MACROVISION2
#define HWI_TVENC_MACROVISION2_TOG          
#define BP_TVENC_MACROVISION2_DATA          0
#define BM_TVENC_MACROVISION2_DATA          0xffffffff
#define BF_TVENC_MACROVISION2_DATA(v)       (((v) & 0xffffffff) << 0)
#define BFM_TVENC_MACROVISION2_DATA(v)      BM_TVENC_MACROVISION2_DATA
#define BF_TVENC_MACROVISION2_DATA_V(e)     BF_TVENC_MACROVISION2_DATA(BV_TVENC_MACROVISION2_DATA__##e)
#define BFM_TVENC_MACROVISION2_DATA_V(v)    BM_TVENC_MACROVISION2_DATA

#define HW_TVENC_MACROVISION3               HW(TVENC_MACROVISION3)
#define HWA_TVENC_MACROVISION3              (0x80038000 + 0x180)
#define HWT_TVENC_MACROVISION3              HWIO_32_RW
#define HWN_TVENC_MACROVISION3              TVENC_MACROVISION3
#define HWI_TVENC_MACROVISION3              
#define HW_TVENC_MACROVISION3_SET           HW(TVENC_MACROVISION3_SET)
#define HWA_TVENC_MACROVISION3_SET          (HWA_TVENC_MACROVISION3 + 0x4)
#define HWT_TVENC_MACROVISION3_SET          HWIO_32_WO
#define HWN_TVENC_MACROVISION3_SET          TVENC_MACROVISION3
#define HWI_TVENC_MACROVISION3_SET          
#define HW_TVENC_MACROVISION3_CLR           HW(TVENC_MACROVISION3_CLR)
#define HWA_TVENC_MACROVISION3_CLR          (HWA_TVENC_MACROVISION3 + 0x8)
#define HWT_TVENC_MACROVISION3_CLR          HWIO_32_WO
#define HWN_TVENC_MACROVISION3_CLR          TVENC_MACROVISION3
#define HWI_TVENC_MACROVISION3_CLR          
#define HW_TVENC_MACROVISION3_TOG           HW(TVENC_MACROVISION3_TOG)
#define HWA_TVENC_MACROVISION3_TOG          (HWA_TVENC_MACROVISION3 + 0xc)
#define HWT_TVENC_MACROVISION3_TOG          HWIO_32_WO
#define HWN_TVENC_MACROVISION3_TOG          TVENC_MACROVISION3
#define HWI_TVENC_MACROVISION3_TOG          
#define BP_TVENC_MACROVISION3_DATA          0
#define BM_TVENC_MACROVISION3_DATA          0xffffffff
#define BF_TVENC_MACROVISION3_DATA(v)       (((v) & 0xffffffff) << 0)
#define BFM_TVENC_MACROVISION3_DATA(v)      BM_TVENC_MACROVISION3_DATA
#define BF_TVENC_MACROVISION3_DATA_V(e)     BF_TVENC_MACROVISION3_DATA(BV_TVENC_MACROVISION3_DATA__##e)
#define BFM_TVENC_MACROVISION3_DATA_V(v)    BM_TVENC_MACROVISION3_DATA

#define HW_TVENC_MACROVISION4                   HW(TVENC_MACROVISION4)
#define HWA_TVENC_MACROVISION4                  (0x80038000 + 0x190)
#define HWT_TVENC_MACROVISION4                  HWIO_32_RW
#define HWN_TVENC_MACROVISION4                  TVENC_MACROVISION4
#define HWI_TVENC_MACROVISION4                  
#define HW_TVENC_MACROVISION4_SET               HW(TVENC_MACROVISION4_SET)
#define HWA_TVENC_MACROVISION4_SET              (HWA_TVENC_MACROVISION4 + 0x4)
#define HWT_TVENC_MACROVISION4_SET              HWIO_32_WO
#define HWN_TVENC_MACROVISION4_SET              TVENC_MACROVISION4
#define HWI_TVENC_MACROVISION4_SET              
#define HW_TVENC_MACROVISION4_CLR               HW(TVENC_MACROVISION4_CLR)
#define HWA_TVENC_MACROVISION4_CLR              (HWA_TVENC_MACROVISION4 + 0x8)
#define HWT_TVENC_MACROVISION4_CLR              HWIO_32_WO
#define HWN_TVENC_MACROVISION4_CLR              TVENC_MACROVISION4
#define HWI_TVENC_MACROVISION4_CLR              
#define HW_TVENC_MACROVISION4_TOG               HW(TVENC_MACROVISION4_TOG)
#define HWA_TVENC_MACROVISION4_TOG              (HWA_TVENC_MACROVISION4 + 0xc)
#define HWT_TVENC_MACROVISION4_TOG              HWIO_32_WO
#define HWN_TVENC_MACROVISION4_TOG              TVENC_MACROVISION4
#define HWI_TVENC_MACROVISION4_TOG              
#define BP_TVENC_MACROVISION4_RSRVD2            24
#define BM_TVENC_MACROVISION4_RSRVD2            0xff000000
#define BF_TVENC_MACROVISION4_RSRVD2(v)         (((v) & 0xff) << 24)
#define BFM_TVENC_MACROVISION4_RSRVD2(v)        BM_TVENC_MACROVISION4_RSRVD2
#define BF_TVENC_MACROVISION4_RSRVD2_V(e)       BF_TVENC_MACROVISION4_RSRVD2(BV_TVENC_MACROVISION4_RSRVD2__##e)
#define BFM_TVENC_MACROVISION4_RSRVD2_V(v)      BM_TVENC_MACROVISION4_RSRVD2
#define BP_TVENC_MACROVISION4_MACV_TST          16
#define BM_TVENC_MACROVISION4_MACV_TST          0xff0000
#define BF_TVENC_MACROVISION4_MACV_TST(v)       (((v) & 0xff) << 16)
#define BFM_TVENC_MACROVISION4_MACV_TST(v)      BM_TVENC_MACROVISION4_MACV_TST
#define BF_TVENC_MACROVISION4_MACV_TST_V(e)     BF_TVENC_MACROVISION4_MACV_TST(BV_TVENC_MACROVISION4_MACV_TST__##e)
#define BFM_TVENC_MACROVISION4_MACV_TST_V(v)    BM_TVENC_MACROVISION4_MACV_TST
#define BP_TVENC_MACROVISION4_RSRVD1            11
#define BM_TVENC_MACROVISION4_RSRVD1            0xf800
#define BF_TVENC_MACROVISION4_RSRVD1(v)         (((v) & 0x1f) << 11)
#define BFM_TVENC_MACROVISION4_RSRVD1(v)        BM_TVENC_MACROVISION4_RSRVD1
#define BF_TVENC_MACROVISION4_RSRVD1_V(e)       BF_TVENC_MACROVISION4_RSRVD1(BV_TVENC_MACROVISION4_RSRVD1__##e)
#define BFM_TVENC_MACROVISION4_RSRVD1_V(v)      BM_TVENC_MACROVISION4_RSRVD1
#define BP_TVENC_MACROVISION4_DATA              0
#define BM_TVENC_MACROVISION4_DATA              0x7ff
#define BF_TVENC_MACROVISION4_DATA(v)           (((v) & 0x7ff) << 0)
#define BFM_TVENC_MACROVISION4_DATA(v)          BM_TVENC_MACROVISION4_DATA
#define BF_TVENC_MACROVISION4_DATA_V(e)         BF_TVENC_MACROVISION4_DATA(BV_TVENC_MACROVISION4_DATA__##e)
#define BFM_TVENC_MACROVISION4_DATA_V(v)        BM_TVENC_MACROVISION4_DATA

#define HW_TVENC_DACCTRL                            HW(TVENC_DACCTRL)
#define HWA_TVENC_DACCTRL                           (0x80038000 + 0x1a0)
#define HWT_TVENC_DACCTRL                           HWIO_32_RW
#define HWN_TVENC_DACCTRL                           TVENC_DACCTRL
#define HWI_TVENC_DACCTRL                           
#define HW_TVENC_DACCTRL_SET                        HW(TVENC_DACCTRL_SET)
#define HWA_TVENC_DACCTRL_SET                       (HWA_TVENC_DACCTRL + 0x4)
#define HWT_TVENC_DACCTRL_SET                       HWIO_32_WO
#define HWN_TVENC_DACCTRL_SET                       TVENC_DACCTRL
#define HWI_TVENC_DACCTRL_SET                       
#define HW_TVENC_DACCTRL_CLR                        HW(TVENC_DACCTRL_CLR)
#define HWA_TVENC_DACCTRL_CLR                       (HWA_TVENC_DACCTRL + 0x8)
#define HWT_TVENC_DACCTRL_CLR                       HWIO_32_WO
#define HWN_TVENC_DACCTRL_CLR                       TVENC_DACCTRL
#define HWI_TVENC_DACCTRL_CLR                       
#define HW_TVENC_DACCTRL_TOG                        HW(TVENC_DACCTRL_TOG)
#define HWA_TVENC_DACCTRL_TOG                       (HWA_TVENC_DACCTRL + 0xc)
#define HWT_TVENC_DACCTRL_TOG                       HWIO_32_WO
#define HWN_TVENC_DACCTRL_TOG                       TVENC_DACCTRL
#define HWI_TVENC_DACCTRL_TOG                       
#define BP_TVENC_DACCTRL_TEST3                      31
#define BM_TVENC_DACCTRL_TEST3                      0x80000000
#define BF_TVENC_DACCTRL_TEST3(v)                   (((v) & 0x1) << 31)
#define BFM_TVENC_DACCTRL_TEST3(v)                  BM_TVENC_DACCTRL_TEST3
#define BF_TVENC_DACCTRL_TEST3_V(e)                 BF_TVENC_DACCTRL_TEST3(BV_TVENC_DACCTRL_TEST3__##e)
#define BFM_TVENC_DACCTRL_TEST3_V(v)                BM_TVENC_DACCTRL_TEST3
#define BP_TVENC_DACCTRL_RSRVD1                     30
#define BM_TVENC_DACCTRL_RSRVD1                     0x40000000
#define BF_TVENC_DACCTRL_RSRVD1(v)                  (((v) & 0x1) << 30)
#define BFM_TVENC_DACCTRL_RSRVD1(v)                 BM_TVENC_DACCTRL_RSRVD1
#define BF_TVENC_DACCTRL_RSRVD1_V(e)                BF_TVENC_DACCTRL_RSRVD1(BV_TVENC_DACCTRL_RSRVD1__##e)
#define BFM_TVENC_DACCTRL_RSRVD1_V(v)               BM_TVENC_DACCTRL_RSRVD1
#define BP_TVENC_DACCTRL_RSRVD2                     29
#define BM_TVENC_DACCTRL_RSRVD2                     0x20000000
#define BF_TVENC_DACCTRL_RSRVD2(v)                  (((v) & 0x1) << 29)
#define BFM_TVENC_DACCTRL_RSRVD2(v)                 BM_TVENC_DACCTRL_RSRVD2
#define BF_TVENC_DACCTRL_RSRVD2_V(e)                BF_TVENC_DACCTRL_RSRVD2(BV_TVENC_DACCTRL_RSRVD2__##e)
#define BFM_TVENC_DACCTRL_RSRVD2_V(v)               BM_TVENC_DACCTRL_RSRVD2
#define BP_TVENC_DACCTRL_JACK1_DIS_DET_EN           28
#define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN           0x10000000
#define BF_TVENC_DACCTRL_JACK1_DIS_DET_EN(v)        (((v) & 0x1) << 28)
#define BFM_TVENC_DACCTRL_JACK1_DIS_DET_EN(v)       BM_TVENC_DACCTRL_JACK1_DIS_DET_EN
#define BF_TVENC_DACCTRL_JACK1_DIS_DET_EN_V(e)      BF_TVENC_DACCTRL_JACK1_DIS_DET_EN(BV_TVENC_DACCTRL_JACK1_DIS_DET_EN__##e)
#define BFM_TVENC_DACCTRL_JACK1_DIS_DET_EN_V(v)     BM_TVENC_DACCTRL_JACK1_DIS_DET_EN
#define BP_TVENC_DACCTRL_TEST2                      27
#define BM_TVENC_DACCTRL_TEST2                      0x8000000
#define BF_TVENC_DACCTRL_TEST2(v)                   (((v) & 0x1) << 27)
#define BFM_TVENC_DACCTRL_TEST2(v)                  BM_TVENC_DACCTRL_TEST2
#define BF_TVENC_DACCTRL_TEST2_V(e)                 BF_TVENC_DACCTRL_TEST2(BV_TVENC_DACCTRL_TEST2__##e)
#define BFM_TVENC_DACCTRL_TEST2_V(v)                BM_TVENC_DACCTRL_TEST2
#define BP_TVENC_DACCTRL_RSRVD3                     26
#define BM_TVENC_DACCTRL_RSRVD3                     0x4000000
#define BF_TVENC_DACCTRL_RSRVD3(v)                  (((v) & 0x1) << 26)
#define BFM_TVENC_DACCTRL_RSRVD3(v)                 BM_TVENC_DACCTRL_RSRVD3
#define BF_TVENC_DACCTRL_RSRVD3_V(e)                BF_TVENC_DACCTRL_RSRVD3(BV_TVENC_DACCTRL_RSRVD3__##e)
#define BFM_TVENC_DACCTRL_RSRVD3_V(v)               BM_TVENC_DACCTRL_RSRVD3
#define BP_TVENC_DACCTRL_RSRVD4                     25
#define BM_TVENC_DACCTRL_RSRVD4                     0x2000000
#define BF_TVENC_DACCTRL_RSRVD4(v)                  (((v) & 0x1) << 25)
#define BFM_TVENC_DACCTRL_RSRVD4(v)                 BM_TVENC_DACCTRL_RSRVD4
#define BF_TVENC_DACCTRL_RSRVD4_V(e)                BF_TVENC_DACCTRL_RSRVD4(BV_TVENC_DACCTRL_RSRVD4__##e)
#define BFM_TVENC_DACCTRL_RSRVD4_V(v)               BM_TVENC_DACCTRL_RSRVD4
#define BP_TVENC_DACCTRL_JACK1_DET_EN               24
#define BM_TVENC_DACCTRL_JACK1_DET_EN               0x1000000
#define BF_TVENC_DACCTRL_JACK1_DET_EN(v)            (((v) & 0x1) << 24)
#define BFM_TVENC_DACCTRL_JACK1_DET_EN(v)           BM_TVENC_DACCTRL_JACK1_DET_EN
#define BF_TVENC_DACCTRL_JACK1_DET_EN_V(e)          BF_TVENC_DACCTRL_JACK1_DET_EN(BV_TVENC_DACCTRL_JACK1_DET_EN__##e)
#define BFM_TVENC_DACCTRL_JACK1_DET_EN_V(v)         BM_TVENC_DACCTRL_JACK1_DET_EN
#define BP_TVENC_DACCTRL_TEST1                      23
#define BM_TVENC_DACCTRL_TEST1                      0x800000
#define BF_TVENC_DACCTRL_TEST1(v)                   (((v) & 0x1) << 23)
#define BFM_TVENC_DACCTRL_TEST1(v)                  BM_TVENC_DACCTRL_TEST1
#define BF_TVENC_DACCTRL_TEST1_V(e)                 BF_TVENC_DACCTRL_TEST1(BV_TVENC_DACCTRL_TEST1__##e)
#define BFM_TVENC_DACCTRL_TEST1_V(v)                BM_TVENC_DACCTRL_TEST1
#define BP_TVENC_DACCTRL_DISABLE_GND_DETECT         22
#define BM_TVENC_DACCTRL_DISABLE_GND_DETECT         0x400000
#define BF_TVENC_DACCTRL_DISABLE_GND_DETECT(v)      (((v) & 0x1) << 22)
#define BFM_TVENC_DACCTRL_DISABLE_GND_DETECT(v)     BM_TVENC_DACCTRL_DISABLE_GND_DETECT
#define BF_TVENC_DACCTRL_DISABLE_GND_DETECT_V(e)    BF_TVENC_DACCTRL_DISABLE_GND_DETECT(BV_TVENC_DACCTRL_DISABLE_GND_DETECT__##e)
#define BFM_TVENC_DACCTRL_DISABLE_GND_DETECT_V(v)   BM_TVENC_DACCTRL_DISABLE_GND_DETECT
#define BP_TVENC_DACCTRL_JACK_DIS_ADJ               20
#define BM_TVENC_DACCTRL_JACK_DIS_ADJ               0x300000
#define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v)            (((v) & 0x3) << 20)
#define BFM_TVENC_DACCTRL_JACK_DIS_ADJ(v)           BM_TVENC_DACCTRL_JACK_DIS_ADJ
#define BF_TVENC_DACCTRL_JACK_DIS_ADJ_V(e)          BF_TVENC_DACCTRL_JACK_DIS_ADJ(BV_TVENC_DACCTRL_JACK_DIS_ADJ__##e)
#define BFM_TVENC_DACCTRL_JACK_DIS_ADJ_V(v)         BM_TVENC_DACCTRL_JACK_DIS_ADJ
#define BP_TVENC_DACCTRL_GAINDN                     19
#define BM_TVENC_DACCTRL_GAINDN                     0x80000
#define BF_TVENC_DACCTRL_GAINDN(v)                  (((v) & 0x1) << 19)
#define BFM_TVENC_DACCTRL_GAINDN(v)                 BM_TVENC_DACCTRL_GAINDN
#define BF_TVENC_DACCTRL_GAINDN_V(e)                BF_TVENC_DACCTRL_GAINDN(BV_TVENC_DACCTRL_GAINDN__##e)
#define BFM_TVENC_DACCTRL_GAINDN_V(v)               BM_TVENC_DACCTRL_GAINDN
#define BP_TVENC_DACCTRL_GAINUP                     18
#define BM_TVENC_DACCTRL_GAINUP                     0x40000
#define BF_TVENC_DACCTRL_GAINUP(v)                  (((v) & 0x1) << 18)
#define BFM_TVENC_DACCTRL_GAINUP(v)                 BM_TVENC_DACCTRL_GAINUP
#define BF_TVENC_DACCTRL_GAINUP_V(e)                BF_TVENC_DACCTRL_GAINUP(BV_TVENC_DACCTRL_GAINUP__##e)
#define BFM_TVENC_DACCTRL_GAINUP_V(v)               BM_TVENC_DACCTRL_GAINUP
#define BP_TVENC_DACCTRL_INVERT_CLK                 17
#define BM_TVENC_DACCTRL_INVERT_CLK                 0x20000
#define BF_TVENC_DACCTRL_INVERT_CLK(v)              (((v) & 0x1) << 17)
#define BFM_TVENC_DACCTRL_INVERT_CLK(v)             BM_TVENC_DACCTRL_INVERT_CLK
#define BF_TVENC_DACCTRL_INVERT_CLK_V(e)            BF_TVENC_DACCTRL_INVERT_CLK(BV_TVENC_DACCTRL_INVERT_CLK__##e)
#define BFM_TVENC_DACCTRL_INVERT_CLK_V(v)           BM_TVENC_DACCTRL_INVERT_CLK
#define BP_TVENC_DACCTRL_SELECT_CLK                 16
#define BM_TVENC_DACCTRL_SELECT_CLK                 0x10000
#define BF_TVENC_DACCTRL_SELECT_CLK(v)              (((v) & 0x1) << 16)
#define BFM_TVENC_DACCTRL_SELECT_CLK(v)             BM_TVENC_DACCTRL_SELECT_CLK
#define BF_TVENC_DACCTRL_SELECT_CLK_V(e)            BF_TVENC_DACCTRL_SELECT_CLK(BV_TVENC_DACCTRL_SELECT_CLK__##e)
#define BFM_TVENC_DACCTRL_SELECT_CLK_V(v)           BM_TVENC_DACCTRL_SELECT_CLK
#define BP_TVENC_DACCTRL_BYPASS_ACT_CASCODE         15
#define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE         0x8000
#define BF_TVENC_DACCTRL_BYPASS_ACT_CASCODE(v)      (((v) & 0x1) << 15)
#define BFM_TVENC_DACCTRL_BYPASS_ACT_CASCODE(v)     BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE
#define BF_TVENC_DACCTRL_BYPASS_ACT_CASCODE_V(e)    BF_TVENC_DACCTRL_BYPASS_ACT_CASCODE(BV_TVENC_DACCTRL_BYPASS_ACT_CASCODE__##e)
#define BFM_TVENC_DACCTRL_BYPASS_ACT_CASCODE_V(v)   BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE
#define BP_TVENC_DACCTRL_RSRVD5                     14
#define BM_TVENC_DACCTRL_RSRVD5                     0x4000
#define BF_TVENC_DACCTRL_RSRVD5(v)                  (((v) & 0x1) << 14)
#define BFM_TVENC_DACCTRL_RSRVD5(v)                 BM_TVENC_DACCTRL_RSRVD5
#define BF_TVENC_DACCTRL_RSRVD5_V(e)                BF_TVENC_DACCTRL_RSRVD5(BV_TVENC_DACCTRL_RSRVD5__##e)
#define BFM_TVENC_DACCTRL_RSRVD5_V(v)               BM_TVENC_DACCTRL_RSRVD5
#define BP_TVENC_DACCTRL_RSRVD6                     13
#define BM_TVENC_DACCTRL_RSRVD6                     0x2000
#define BF_TVENC_DACCTRL_RSRVD6(v)                  (((v) & 0x1) << 13)
#define BFM_TVENC_DACCTRL_RSRVD6(v)                 BM_TVENC_DACCTRL_RSRVD6
#define BF_TVENC_DACCTRL_RSRVD6_V(e)                BF_TVENC_DACCTRL_RSRVD6(BV_TVENC_DACCTRL_RSRVD6__##e)
#define BFM_TVENC_DACCTRL_RSRVD6_V(v)               BM_TVENC_DACCTRL_RSRVD6
#define BP_TVENC_DACCTRL_PWRUP1                     12
#define BM_TVENC_DACCTRL_PWRUP1                     0x1000
#define BF_TVENC_DACCTRL_PWRUP1(v)                  (((v) & 0x1) << 12)
#define BFM_TVENC_DACCTRL_PWRUP1(v)                 BM_TVENC_DACCTRL_PWRUP1
#define BF_TVENC_DACCTRL_PWRUP1_V(e)                BF_TVENC_DACCTRL_PWRUP1(BV_TVENC_DACCTRL_PWRUP1__##e)
#define BFM_TVENC_DACCTRL_PWRUP1_V(v)               BM_TVENC_DACCTRL_PWRUP1
#define BP_TVENC_DACCTRL_WELL_TOVDD                 11
#define BM_TVENC_DACCTRL_WELL_TOVDD                 0x800
#define BF_TVENC_DACCTRL_WELL_TOVDD(v)              (((v) & 0x1) << 11)
#define BFM_TVENC_DACCTRL_WELL_TOVDD(v)             BM_TVENC_DACCTRL_WELL_TOVDD
#define BF_TVENC_DACCTRL_WELL_TOVDD_V(e)            BF_TVENC_DACCTRL_WELL_TOVDD(BV_TVENC_DACCTRL_WELL_TOVDD__##e)
#define BFM_TVENC_DACCTRL_WELL_TOVDD_V(v)           BM_TVENC_DACCTRL_WELL_TOVDD
#define BP_TVENC_DACCTRL_RSRVD7                     10
#define BM_TVENC_DACCTRL_RSRVD7                     0x400
#define BF_TVENC_DACCTRL_RSRVD7(v)                  (((v) & 0x1) << 10)
#define BFM_TVENC_DACCTRL_RSRVD7(v)                 BM_TVENC_DACCTRL_RSRVD7
#define BF_TVENC_DACCTRL_RSRVD7_V(e)                BF_TVENC_DACCTRL_RSRVD7(BV_TVENC_DACCTRL_RSRVD7__##e)
#define BFM_TVENC_DACCTRL_RSRVD7_V(v)               BM_TVENC_DACCTRL_RSRVD7
#define BP_TVENC_DACCTRL_RSRVD8                     9
#define BM_TVENC_DACCTRL_RSRVD8                     0x200
#define BF_TVENC_DACCTRL_RSRVD8(v)                  (((v) & 0x1) << 9)
#define BFM_TVENC_DACCTRL_RSRVD8(v)                 BM_TVENC_DACCTRL_RSRVD8
#define BF_TVENC_DACCTRL_RSRVD8_V(e)                BF_TVENC_DACCTRL_RSRVD8(BV_TVENC_DACCTRL_RSRVD8__##e)
#define BFM_TVENC_DACCTRL_RSRVD8_V(v)               BM_TVENC_DACCTRL_RSRVD8
#define BP_TVENC_DACCTRL_DUMP_TOVDD1                8
#define BM_TVENC_DACCTRL_DUMP_TOVDD1                0x100
#define BF_TVENC_DACCTRL_DUMP_TOVDD1(v)             (((v) & 0x1) << 8)
#define BFM_TVENC_DACCTRL_DUMP_TOVDD1(v)            BM_TVENC_DACCTRL_DUMP_TOVDD1
#define BF_TVENC_DACCTRL_DUMP_TOVDD1_V(e)           BF_TVENC_DACCTRL_DUMP_TOVDD1(BV_TVENC_DACCTRL_DUMP_TOVDD1__##e)
#define BFM_TVENC_DACCTRL_DUMP_TOVDD1_V(v)          BM_TVENC_DACCTRL_DUMP_TOVDD1
#define BP_TVENC_DACCTRL_LOWER_SIGNAL               7
#define BM_TVENC_DACCTRL_LOWER_SIGNAL               0x80
#define BF_TVENC_DACCTRL_LOWER_SIGNAL(v)            (((v) & 0x1) << 7)
#define BFM_TVENC_DACCTRL_LOWER_SIGNAL(v)           BM_TVENC_DACCTRL_LOWER_SIGNAL
#define BF_TVENC_DACCTRL_LOWER_SIGNAL_V(e)          BF_TVENC_DACCTRL_LOWER_SIGNAL(BV_TVENC_DACCTRL_LOWER_SIGNAL__##e)
#define BFM_TVENC_DACCTRL_LOWER_SIGNAL_V(v)         BM_TVENC_DACCTRL_LOWER_SIGNAL
#define BP_TVENC_DACCTRL_RVAL                       4
#define BM_TVENC_DACCTRL_RVAL                       0x70
#define BF_TVENC_DACCTRL_RVAL(v)                    (((v) & 0x7) << 4)
#define BFM_TVENC_DACCTRL_RVAL(v)                   BM_TVENC_DACCTRL_RVAL
#define BF_TVENC_DACCTRL_RVAL_V(e)                  BF_TVENC_DACCTRL_RVAL(BV_TVENC_DACCTRL_RVAL__##e)
#define BFM_TVENC_DACCTRL_RVAL_V(v)                 BM_TVENC_DACCTRL_RVAL
#define BP_TVENC_DACCTRL_NO_INTERNAL_TERM           3
#define BM_TVENC_DACCTRL_NO_INTERNAL_TERM           0x8
#define BF_TVENC_DACCTRL_NO_INTERNAL_TERM(v)        (((v) & 0x1) << 3)
#define BFM_TVENC_DACCTRL_NO_INTERNAL_TERM(v)       BM_TVENC_DACCTRL_NO_INTERNAL_TERM
#define BF_TVENC_DACCTRL_NO_INTERNAL_TERM_V(e)      BF_TVENC_DACCTRL_NO_INTERNAL_TERM(BV_TVENC_DACCTRL_NO_INTERNAL_TERM__##e)
#define BFM_TVENC_DACCTRL_NO_INTERNAL_TERM_V(v)     BM_TVENC_DACCTRL_NO_INTERNAL_TERM
#define BP_TVENC_DACCTRL_HALF_CURRENT               2
#define BM_TVENC_DACCTRL_HALF_CURRENT               0x4
#define BF_TVENC_DACCTRL_HALF_CURRENT(v)            (((v) & 0x1) << 2)
#define BFM_TVENC_DACCTRL_HALF_CURRENT(v)           BM_TVENC_DACCTRL_HALF_CURRENT
#define BF_TVENC_DACCTRL_HALF_CURRENT_V(e)          BF_TVENC_DACCTRL_HALF_CURRENT(BV_TVENC_DACCTRL_HALF_CURRENT__##e)
#define BFM_TVENC_DACCTRL_HALF_CURRENT_V(v)         BM_TVENC_DACCTRL_HALF_CURRENT
#define BP_TVENC_DACCTRL_CASC_ADJ                   0
#define BM_TVENC_DACCTRL_CASC_ADJ                   0x3
#define BF_TVENC_DACCTRL_CASC_ADJ(v)                (((v) & 0x3) << 0)
#define BFM_TVENC_DACCTRL_CASC_ADJ(v)               BM_TVENC_DACCTRL_CASC_ADJ
#define BF_TVENC_DACCTRL_CASC_ADJ_V(e)              BF_TVENC_DACCTRL_CASC_ADJ(BV_TVENC_DACCTRL_CASC_ADJ__##e)
#define BFM_TVENC_DACCTRL_CASC_ADJ_V(v)             BM_TVENC_DACCTRL_CASC_ADJ

#define HW_TVENC_DACSTATUS                          HW(TVENC_DACSTATUS)
#define HWA_TVENC_DACSTATUS                         (0x80038000 + 0x1b0)
#define HWT_TVENC_DACSTATUS                         HWIO_32_RW
#define HWN_TVENC_DACSTATUS                         TVENC_DACSTATUS
#define HWI_TVENC_DACSTATUS                         
#define HW_TVENC_DACSTATUS_SET                      HW(TVENC_DACSTATUS_SET)
#define HWA_TVENC_DACSTATUS_SET                     (HWA_TVENC_DACSTATUS + 0x4)
#define HWT_TVENC_DACSTATUS_SET                     HWIO_32_WO
#define HWN_TVENC_DACSTATUS_SET                     TVENC_DACSTATUS
#define HWI_TVENC_DACSTATUS_SET                     
#define HW_TVENC_DACSTATUS_CLR                      HW(TVENC_DACSTATUS_CLR)
#define HWA_TVENC_DACSTATUS_CLR                     (HWA_TVENC_DACSTATUS + 0x8)
#define HWT_TVENC_DACSTATUS_CLR                     HWIO_32_WO
#define HWN_TVENC_DACSTATUS_CLR                     TVENC_DACSTATUS
#define HWI_TVENC_DACSTATUS_CLR                     
#define HW_TVENC_DACSTATUS_TOG                      HW(TVENC_DACSTATUS_TOG)
#define HWA_TVENC_DACSTATUS_TOG                     (HWA_TVENC_DACSTATUS + 0xc)
#define HWT_TVENC_DACSTATUS_TOG                     HWIO_32_WO
#define HWN_TVENC_DACSTATUS_TOG                     TVENC_DACSTATUS
#define HWI_TVENC_DACSTATUS_TOG                     
#define BP_TVENC_DACSTATUS_RSRVD1                   13
#define BM_TVENC_DACSTATUS_RSRVD1                   0xffffe000
#define BF_TVENC_DACSTATUS_RSRVD1(v)                (((v) & 0x7ffff) << 13)
#define BFM_TVENC_DACSTATUS_RSRVD1(v)               BM_TVENC_DACSTATUS_RSRVD1
#define BF_TVENC_DACSTATUS_RSRVD1_V(e)              BF_TVENC_DACSTATUS_RSRVD1(BV_TVENC_DACSTATUS_RSRVD1__##e)
#define BFM_TVENC_DACSTATUS_RSRVD1_V(v)             BM_TVENC_DACSTATUS_RSRVD1
#define BP_TVENC_DACSTATUS_RSRVD2                   12
#define BM_TVENC_DACSTATUS_RSRVD2                   0x1000
#define BF_TVENC_DACSTATUS_RSRVD2(v)                (((v) & 0x1) << 12)
#define BFM_TVENC_DACSTATUS_RSRVD2(v)               BM_TVENC_DACSTATUS_RSRVD2
#define BF_TVENC_DACSTATUS_RSRVD2_V(e)              BF_TVENC_DACSTATUS_RSRVD2(BV_TVENC_DACSTATUS_RSRVD2__##e)
#define BFM_TVENC_DACSTATUS_RSRVD2_V(v)             BM_TVENC_DACSTATUS_RSRVD2
#define BP_TVENC_DACSTATUS_RSRVD3                   11
#define BM_TVENC_DACSTATUS_RSRVD3                   0x800
#define BF_TVENC_DACSTATUS_RSRVD3(v)                (((v) & 0x1) << 11)
#define BFM_TVENC_DACSTATUS_RSRVD3(v)               BM_TVENC_DACSTATUS_RSRVD3
#define BF_TVENC_DACSTATUS_RSRVD3_V(e)              BF_TVENC_DACSTATUS_RSRVD3(BV_TVENC_DACSTATUS_RSRVD3__##e)
#define BFM_TVENC_DACSTATUS_RSRVD3_V(v)             BM_TVENC_DACSTATUS_RSRVD3
#define BP_TVENC_DACSTATUS_JACK1_DET_STATUS         10
#define BM_TVENC_DACSTATUS_JACK1_DET_STATUS         0x400
#define BF_TVENC_DACSTATUS_JACK1_DET_STATUS(v)      (((v) & 0x1) << 10)
#define BFM_TVENC_DACSTATUS_JACK1_DET_STATUS(v)     BM_TVENC_DACSTATUS_JACK1_DET_STATUS
#define BF_TVENC_DACSTATUS_JACK1_DET_STATUS_V(e)    BF_TVENC_DACSTATUS_JACK1_DET_STATUS(BV_TVENC_DACSTATUS_JACK1_DET_STATUS__##e)
#define BFM_TVENC_DACSTATUS_JACK1_DET_STATUS_V(v)   BM_TVENC_DACSTATUS_JACK1_DET_STATUS
#define BP_TVENC_DACSTATUS_RSRVD4                   9
#define BM_TVENC_DACSTATUS_RSRVD4                   0x200
#define BF_TVENC_DACSTATUS_RSRVD4(v)                (((v) & 0x1) << 9)
#define BFM_TVENC_DACSTATUS_RSRVD4(v)               BM_TVENC_DACSTATUS_RSRVD4
#define BF_TVENC_DACSTATUS_RSRVD4_V(e)              BF_TVENC_DACSTATUS_RSRVD4(BV_TVENC_DACSTATUS_RSRVD4__##e)
#define BFM_TVENC_DACSTATUS_RSRVD4_V(v)             BM_TVENC_DACSTATUS_RSRVD4
#define BP_TVENC_DACSTATUS_RSRVD5                   8
#define BM_TVENC_DACSTATUS_RSRVD5                   0x100
#define BF_TVENC_DACSTATUS_RSRVD5(v)                (((v) & 0x1) << 8)
#define BFM_TVENC_DACSTATUS_RSRVD5(v)               BM_TVENC_DACSTATUS_RSRVD5
#define BF_TVENC_DACSTATUS_RSRVD5_V(e)              BF_TVENC_DACSTATUS_RSRVD5(BV_TVENC_DACSTATUS_RSRVD5__##e)
#define BFM_TVENC_DACSTATUS_RSRVD5_V(v)             BM_TVENC_DACSTATUS_RSRVD5
#define BP_TVENC_DACSTATUS_JACK1_GROUNDED           7
#define BM_TVENC_DACSTATUS_JACK1_GROUNDED           0x80
#define BF_TVENC_DACSTATUS_JACK1_GROUNDED(v)        (((v) & 0x1) << 7)
#define BFM_TVENC_DACSTATUS_JACK1_GROUNDED(v)       BM_TVENC_DACSTATUS_JACK1_GROUNDED
#define BF_TVENC_DACSTATUS_JACK1_GROUNDED_V(e)      BF_TVENC_DACSTATUS_JACK1_GROUNDED(BV_TVENC_DACSTATUS_JACK1_GROUNDED__##e)
#define BFM_TVENC_DACSTATUS_JACK1_GROUNDED_V(v)     BM_TVENC_DACSTATUS_JACK1_GROUNDED
#define BP_TVENC_DACSTATUS_RSRVD6                   6
#define BM_TVENC_DACSTATUS_RSRVD6                   0x40
#define BF_TVENC_DACSTATUS_RSRVD6(v)                (((v) & 0x1) << 6)
#define BFM_TVENC_DACSTATUS_RSRVD6(v)               BM_TVENC_DACSTATUS_RSRVD6
#define BF_TVENC_DACSTATUS_RSRVD6_V(e)              BF_TVENC_DACSTATUS_RSRVD6(BV_TVENC_DACSTATUS_RSRVD6__##e)
#define BFM_TVENC_DACSTATUS_RSRVD6_V(v)             BM_TVENC_DACSTATUS_RSRVD6
#define BP_TVENC_DACSTATUS_RSRVD7                   5
#define BM_TVENC_DACSTATUS_RSRVD7                   0x20
#define BF_TVENC_DACSTATUS_RSRVD7(v)                (((v) & 0x1) << 5)
#define BFM_TVENC_DACSTATUS_RSRVD7(v)               BM_TVENC_DACSTATUS_RSRVD7
#define BF_TVENC_DACSTATUS_RSRVD7_V(e)              BF_TVENC_DACSTATUS_RSRVD7(BV_TVENC_DACSTATUS_RSRVD7__##e)
#define BFM_TVENC_DACSTATUS_RSRVD7_V(v)             BM_TVENC_DACSTATUS_RSRVD7
#define BP_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ        4
#define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ        0x10
#define BF_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ(v)     (((v) & 0x1) << 4)
#define BFM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ(v)    BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ
#define BF_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ_V(e)   BF_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ(BV_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ__##e)
#define BFM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ_V(v)  BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ
#define BP_TVENC_DACSTATUS_RSRVD8                   3
#define BM_TVENC_DACSTATUS_RSRVD8                   0x8
#define BF_TVENC_DACSTATUS_RSRVD8(v)                (((v) & 0x1) << 3)
#define BFM_TVENC_DACSTATUS_RSRVD8(v)               BM_TVENC_DACSTATUS_RSRVD8
#define BF_TVENC_DACSTATUS_RSRVD8_V(e)              BF_TVENC_DACSTATUS_RSRVD8(BV_TVENC_DACSTATUS_RSRVD8__##e)
#define BFM_TVENC_DACSTATUS_RSRVD8_V(v)             BM_TVENC_DACSTATUS_RSRVD8
#define BP_TVENC_DACSTATUS_RSRVD9                   2
#define BM_TVENC_DACSTATUS_RSRVD9                   0x4
#define BF_TVENC_DACSTATUS_RSRVD9(v)                (((v) & 0x1) << 2)
#define BFM_TVENC_DACSTATUS_RSRVD9(v)               BM_TVENC_DACSTATUS_RSRVD9
#define BF_TVENC_DACSTATUS_RSRVD9_V(e)              BF_TVENC_DACSTATUS_RSRVD9(BV_TVENC_DACSTATUS_RSRVD9__##e)
#define BFM_TVENC_DACSTATUS_RSRVD9_V(v)             BM_TVENC_DACSTATUS_RSRVD9
#define BP_TVENC_DACSTATUS_JACK1_DET_IRQ            1
#define BM_TVENC_DACSTATUS_JACK1_DET_IRQ            0x2
#define BF_TVENC_DACSTATUS_JACK1_DET_IRQ(v)         (((v) & 0x1) << 1)
#define BFM_TVENC_DACSTATUS_JACK1_DET_IRQ(v)        BM_TVENC_DACSTATUS_JACK1_DET_IRQ
#define BF_TVENC_DACSTATUS_JACK1_DET_IRQ_V(e)       BF_TVENC_DACSTATUS_JACK1_DET_IRQ(BV_TVENC_DACSTATUS_JACK1_DET_IRQ__##e)
#define BFM_TVENC_DACSTATUS_JACK1_DET_IRQ_V(v)      BM_TVENC_DACSTATUS_JACK1_DET_IRQ
#define BP_TVENC_DACSTATUS_ENIRQ_JACK               0
#define BM_TVENC_DACSTATUS_ENIRQ_JACK               0x1
#define BF_TVENC_DACSTATUS_ENIRQ_JACK(v)            (((v) & 0x1) << 0)
#define BFM_TVENC_DACSTATUS_ENIRQ_JACK(v)           BM_TVENC_DACSTATUS_ENIRQ_JACK
#define BF_TVENC_DACSTATUS_ENIRQ_JACK_V(e)          BF_TVENC_DACSTATUS_ENIRQ_JACK(BV_TVENC_DACSTATUS_ENIRQ_JACK__##e)
#define BFM_TVENC_DACSTATUS_ENIRQ_JACK_V(v)         BM_TVENC_DACSTATUS_ENIRQ_JACK

#define HW_TVENC_VDACTEST                               HW(TVENC_VDACTEST)
#define HWA_TVENC_VDACTEST                              (0x80038000 + 0x1c0)
#define HWT_TVENC_VDACTEST                              HWIO_32_RW
#define HWN_TVENC_VDACTEST                              TVENC_VDACTEST
#define HWI_TVENC_VDACTEST                              
#define HW_TVENC_VDACTEST_SET                           HW(TVENC_VDACTEST_SET)
#define HWA_TVENC_VDACTEST_SET                          (HWA_TVENC_VDACTEST + 0x4)
#define HWT_TVENC_VDACTEST_SET                          HWIO_32_WO
#define HWN_TVENC_VDACTEST_SET                          TVENC_VDACTEST
#define HWI_TVENC_VDACTEST_SET                          
#define HW_TVENC_VDACTEST_CLR                           HW(TVENC_VDACTEST_CLR)
#define HWA_TVENC_VDACTEST_CLR                          (HWA_TVENC_VDACTEST + 0x8)
#define HWT_TVENC_VDACTEST_CLR                          HWIO_32_WO
#define HWN_TVENC_VDACTEST_CLR                          TVENC_VDACTEST
#define HWI_TVENC_VDACTEST_CLR                          
#define HW_TVENC_VDACTEST_TOG                           HW(TVENC_VDACTEST_TOG)
#define HWA_TVENC_VDACTEST_TOG                          (HWA_TVENC_VDACTEST + 0xc)
#define HWT_TVENC_VDACTEST_TOG                          HWIO_32_WO
#define HWN_TVENC_VDACTEST_TOG                          TVENC_VDACTEST
#define HWI_TVENC_VDACTEST_TOG                          
#define BP_TVENC_VDACTEST_RSRVD1                        14
#define BM_TVENC_VDACTEST_RSRVD1                        0xffffc000
#define BF_TVENC_VDACTEST_RSRVD1(v)                     (((v) & 0x3ffff) << 14)
#define BFM_TVENC_VDACTEST_RSRVD1(v)                    BM_TVENC_VDACTEST_RSRVD1
#define BF_TVENC_VDACTEST_RSRVD1_V(e)                   BF_TVENC_VDACTEST_RSRVD1(BV_TVENC_VDACTEST_RSRVD1__##e)
#define BFM_TVENC_VDACTEST_RSRVD1_V(v)                  BM_TVENC_VDACTEST_RSRVD1
#define BP_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN           13
#define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN           0x2000
#define BF_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN(v)        (((v) & 0x1) << 13)
#define BFM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN(v)       BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN
#define BF_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN_V(e)      BF_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN(BV_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN__##e)
#define BFM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN_V(v)     BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN
#define BP_TVENC_VDACTEST_BYPASS_PIX_INT                12
#define BM_TVENC_VDACTEST_BYPASS_PIX_INT                0x1000
#define BF_TVENC_VDACTEST_BYPASS_PIX_INT(v)             (((v) & 0x1) << 12)
#define BFM_TVENC_VDACTEST_BYPASS_PIX_INT(v)            BM_TVENC_VDACTEST_BYPASS_PIX_INT
#define BF_TVENC_VDACTEST_BYPASS_PIX_INT_V(e)           BF_TVENC_VDACTEST_BYPASS_PIX_INT(BV_TVENC_VDACTEST_BYPASS_PIX_INT__##e)
#define BFM_TVENC_VDACTEST_BYPASS_PIX_INT_V(v)          BM_TVENC_VDACTEST_BYPASS_PIX_INT
#define BP_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP          11
#define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP          0x800
#define BF_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP(v)       (((v) & 0x1) << 11)
#define BFM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP(v)      BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP
#define BF_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP_V(e)     BF_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP(BV_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP__##e)
#define BFM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP_V(v)    BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP
#define BP_TVENC_VDACTEST_TEST_FIFO_FULL                10
#define BM_TVENC_VDACTEST_TEST_FIFO_FULL                0x400
#define BF_TVENC_VDACTEST_TEST_FIFO_FULL(v)             (((v) & 0x1) << 10)
#define BFM_TVENC_VDACTEST_TEST_FIFO_FULL(v)            BM_TVENC_VDACTEST_TEST_FIFO_FULL
#define BF_TVENC_VDACTEST_TEST_FIFO_FULL_V(e)           BF_TVENC_VDACTEST_TEST_FIFO_FULL(BV_TVENC_VDACTEST_TEST_FIFO_FULL__##e)
#define BFM_TVENC_VDACTEST_TEST_FIFO_FULL_V(v)          BM_TVENC_VDACTEST_TEST_FIFO_FULL
#define BP_TVENC_VDACTEST_DATA                          0
#define BM_TVENC_VDACTEST_DATA                          0x3ff
#define BF_TVENC_VDACTEST_DATA(v)                       (((v) & 0x3ff) << 0)
#define BFM_TVENC_VDACTEST_DATA(v)                      BM_TVENC_VDACTEST_DATA
#define BF_TVENC_VDACTEST_DATA_V(e)                     BF_TVENC_VDACTEST_DATA(BV_TVENC_VDACTEST_DATA__##e)
#define BFM_TVENC_VDACTEST_DATA_V(v)                    BM_TVENC_VDACTEST_DATA

#define HW_TVENC_VERSION                HW(TVENC_VERSION)
#define HWA_TVENC_VERSION               (0x80038000 + 0x1d0)
#define HWT_TVENC_VERSION               HWIO_32_RW
#define HWN_TVENC_VERSION               TVENC_VERSION
#define HWI_TVENC_VERSION               
#define BP_TVENC_VERSION_MAJOR          24
#define BM_TVENC_VERSION_MAJOR          0xff000000
#define BF_TVENC_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
#define BFM_TVENC_VERSION_MAJOR(v)      BM_TVENC_VERSION_MAJOR
#define BF_TVENC_VERSION_MAJOR_V(e)     BF_TVENC_VERSION_MAJOR(BV_TVENC_VERSION_MAJOR__##e)
#define BFM_TVENC_VERSION_MAJOR_V(v)    BM_TVENC_VERSION_MAJOR
#define BP_TVENC_VERSION_MINOR          16
#define BM_TVENC_VERSION_MINOR          0xff0000
#define BF_TVENC_VERSION_MINOR(v)       (((v) & 0xff) << 16)
#define BFM_TVENC_VERSION_MINOR(v)      BM_TVENC_VERSION_MINOR
#define BF_TVENC_VERSION_MINOR_V(e)     BF_TVENC_VERSION_MINOR(BV_TVENC_VERSION_MINOR__##e)
#define BFM_TVENC_VERSION_MINOR_V(v)    BM_TVENC_VERSION_MINOR
#define BP_TVENC_VERSION_STEP           0
#define BM_TVENC_VERSION_STEP           0xffff
#define BF_TVENC_VERSION_STEP(v)        (((v) & 0xffff) << 0)
#define BFM_TVENC_VERSION_STEP(v)       BM_TVENC_VERSION_STEP
#define BF_TVENC_VERSION_STEP_V(e)      BF_TVENC_VERSION_STEP(BV_TVENC_VERSION_STEP__##e)
#define BFM_TVENC_VERSION_STEP_V(v)     BM_TVENC_VERSION_STEP

#endif /* __HEADERGEN_IMX233_TVENC_H__*/
