/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * imx233 version: 2.4.0
 * imx233 authors: Amaury Pouly
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_IMX233_SYDMA_H__
#define __HEADERGEN_IMX233_SYDMA_H__

#define HW_SYDMA_CTRL                           HW(SYDMA_CTRL)
#define HWA_SYDMA_CTRL                          (0x80026000 + 0x0)
#define HWT_SYDMA_CTRL                          HWIO_32_RW
#define HWN_SYDMA_CTRL                          SYDMA_CTRL
#define HWI_SYDMA_CTRL                          
#define HW_SYDMA_CTRL_SET                       HW(SYDMA_CTRL_SET)
#define HWA_SYDMA_CTRL_SET                      (HWA_SYDMA_CTRL + 0x4)
#define HWT_SYDMA_CTRL_SET                      HWIO_32_WO
#define HWN_SYDMA_CTRL_SET                      SYDMA_CTRL
#define HWI_SYDMA_CTRL_SET                      
#define HW_SYDMA_CTRL_CLR                       HW(SYDMA_CTRL_CLR)
#define HWA_SYDMA_CTRL_CLR                      (HWA_SYDMA_CTRL + 0x8)
#define HWT_SYDMA_CTRL_CLR                      HWIO_32_WO
#define HWN_SYDMA_CTRL_CLR                      SYDMA_CTRL
#define HWI_SYDMA_CTRL_CLR                      
#define HW_SYDMA_CTRL_TOG                       HW(SYDMA_CTRL_TOG)
#define HWA_SYDMA_CTRL_TOG                      (HWA_SYDMA_CTRL + 0xc)
#define HWT_SYDMA_CTRL_TOG                      HWIO_32_WO
#define HWN_SYDMA_CTRL_TOG                      SYDMA_CTRL
#define HWI_SYDMA_CTRL_TOG                      
#define BP_SYDMA_CTRL_SFTRST                    31
#define BM_SYDMA_CTRL_SFTRST                    0x80000000
#define BV_SYDMA_CTRL_SFTRST__RUN               0x0
#define BV_SYDMA_CTRL_SFTRST__RESET             0x1
#define BF_SYDMA_CTRL_SFTRST(v)                 (((v) & 0x1) << 31)
#define BFM_SYDMA_CTRL_SFTRST(v)                BM_SYDMA_CTRL_SFTRST
#define BF_SYDMA_CTRL_SFTRST_V(e)               BF_SYDMA_CTRL_SFTRST(BV_SYDMA_CTRL_SFTRST__##e)
#define BFM_SYDMA_CTRL_SFTRST_V(v)              BM_SYDMA_CTRL_SFTRST
#define BP_SYDMA_CTRL_CLKGATE                   30
#define BM_SYDMA_CTRL_CLKGATE                   0x40000000
#define BV_SYDMA_CTRL_CLKGATE__RUN              0x0
#define BV_SYDMA_CTRL_CLKGATE__NO_CLKS          0x1
#define BF_SYDMA_CTRL_CLKGATE(v)                (((v) & 0x1) << 30)
#define BFM_SYDMA_CTRL_CLKGATE(v)               BM_SYDMA_CTRL_CLKGATE
#define BF_SYDMA_CTRL_CLKGATE_V(e)              BF_SYDMA_CTRL_CLKGATE(BV_SYDMA_CTRL_CLKGATE__##e)
#define BFM_SYDMA_CTRL_CLKGATE_V(v)             BM_SYDMA_CTRL_CLKGATE
#define BP_SYDMA_CTRL_RSVD1                     10
#define BM_SYDMA_CTRL_RSVD1                     0x3ffffc00
#define BF_SYDMA_CTRL_RSVD1(v)                  (((v) & 0xfffff) << 10)
#define BFM_SYDMA_CTRL_RSVD1(v)                 BM_SYDMA_CTRL_RSVD1
#define BF_SYDMA_CTRL_RSVD1_V(e)                BF_SYDMA_CTRL_RSVD1(BV_SYDMA_CTRL_RSVD1__##e)
#define BFM_SYDMA_CTRL_RSVD1_V(v)               BM_SYDMA_CTRL_RSVD1
#define BP_SYDMA_CTRL_COMPLETE_IRQ_EN           9
#define BM_SYDMA_CTRL_COMPLETE_IRQ_EN           0x200
#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__DISABLED 0x0
#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__ENABLED  0x1
#define BF_SYDMA_CTRL_COMPLETE_IRQ_EN(v)        (((v) & 0x1) << 9)
#define BFM_SYDMA_CTRL_COMPLETE_IRQ_EN(v)       BM_SYDMA_CTRL_COMPLETE_IRQ_EN
#define BF_SYDMA_CTRL_COMPLETE_IRQ_EN_V(e)      BF_SYDMA_CTRL_COMPLETE_IRQ_EN(BV_SYDMA_CTRL_COMPLETE_IRQ_EN__##e)
#define BFM_SYDMA_CTRL_COMPLETE_IRQ_EN_V(v)     BM_SYDMA_CTRL_COMPLETE_IRQ_EN
#define BP_SYDMA_CTRL_RSVD0                     3
#define BM_SYDMA_CTRL_RSVD0                     0x1f8
#define BF_SYDMA_CTRL_RSVD0(v)                  (((v) & 0x3f) << 3)
#define BFM_SYDMA_CTRL_RSVD0(v)                 BM_SYDMA_CTRL_RSVD0
#define BF_SYDMA_CTRL_RSVD0_V(e)                BF_SYDMA_CTRL_RSVD0(BV_SYDMA_CTRL_RSVD0__##e)
#define BFM_SYDMA_CTRL_RSVD0_V(v)               BM_SYDMA_CTRL_RSVD0
#define BP_SYDMA_CTRL_ERROR_IRQ                 2
#define BM_SYDMA_CTRL_ERROR_IRQ                 0x4
#define BF_SYDMA_CTRL_ERROR_IRQ(v)              (((v) & 0x1) << 2)
#define BFM_SYDMA_CTRL_ERROR_IRQ(v)             BM_SYDMA_CTRL_ERROR_IRQ
#define BF_SYDMA_CTRL_ERROR_IRQ_V(e)            BF_SYDMA_CTRL_ERROR_IRQ(BV_SYDMA_CTRL_ERROR_IRQ__##e)
#define BFM_SYDMA_CTRL_ERROR_IRQ_V(v)           BM_SYDMA_CTRL_ERROR_IRQ
#define BP_SYDMA_CTRL_COMPLETE_IRQ              1
#define BM_SYDMA_CTRL_COMPLETE_IRQ              0x2
#define BF_SYDMA_CTRL_COMPLETE_IRQ(v)           (((v) & 0x1) << 1)
#define BFM_SYDMA_CTRL_COMPLETE_IRQ(v)          BM_SYDMA_CTRL_COMPLETE_IRQ
#define BF_SYDMA_CTRL_COMPLETE_IRQ_V(e)         BF_SYDMA_CTRL_COMPLETE_IRQ(BV_SYDMA_CTRL_COMPLETE_IRQ__##e)
#define BFM_SYDMA_CTRL_COMPLETE_IRQ_V(v)        BM_SYDMA_CTRL_COMPLETE_IRQ
#define BP_SYDMA_CTRL_RUN                       0
#define BM_SYDMA_CTRL_RUN                       0x1
#define BV_SYDMA_CTRL_RUN__HALT                 0x0
#define BV_SYDMA_CTRL_RUN__RUN                  0x1
#define BF_SYDMA_CTRL_RUN(v)                    (((v) & 0x1) << 0)
#define BFM_SYDMA_CTRL_RUN(v)                   BM_SYDMA_CTRL_RUN
#define BF_SYDMA_CTRL_RUN_V(e)                  BF_SYDMA_CTRL_RUN(BV_SYDMA_CTRL_RUN__##e)
#define BFM_SYDMA_CTRL_RUN_V(v)                 BM_SYDMA_CTRL_RUN

#define HW_SYDMA_RADDR                  HW(SYDMA_RADDR)
#define HWA_SYDMA_RADDR                 (0x80026000 + 0x10)
#define HWT_SYDMA_RADDR                 HWIO_32_RW
#define HWN_SYDMA_RADDR                 SYDMA_RADDR
#define HWI_SYDMA_RADDR                 
#define BP_SYDMA_RADDR_RSRC_ADDR        0
#define BM_SYDMA_RADDR_RSRC_ADDR        0xffffffff
#define BF_SYDMA_RADDR_RSRC_ADDR(v)     (((v) & 0xffffffff) << 0)
#define BFM_SYDMA_RADDR_RSRC_ADDR(v)    BM_SYDMA_RADDR_RSRC_ADDR
#define BF_SYDMA_RADDR_RSRC_ADDR_V(e)   BF_SYDMA_RADDR_RSRC_ADDR(BV_SYDMA_RADDR_RSRC_ADDR__##e)
#define BFM_SYDMA_RADDR_RSRC_ADDR_V(v)  BM_SYDMA_RADDR_RSRC_ADDR

#define HW_SYDMA_WADDR                  HW(SYDMA_WADDR)
#define HWA_SYDMA_WADDR                 (0x80026000 + 0x20)
#define HWT_SYDMA_WADDR                 HWIO_32_RW
#define HWN_SYDMA_WADDR                 SYDMA_WADDR
#define HWI_SYDMA_WADDR                 
#define BP_SYDMA_WADDR_WSRC_ADDR        0
#define BM_SYDMA_WADDR_WSRC_ADDR        0xffffffff
#define BF_SYDMA_WADDR_WSRC_ADDR(v)     (((v) & 0xffffffff) << 0)
#define BFM_SYDMA_WADDR_WSRC_ADDR(v)    BM_SYDMA_WADDR_WSRC_ADDR
#define BF_SYDMA_WADDR_WSRC_ADDR_V(e)   BF_SYDMA_WADDR_WSRC_ADDR(BV_SYDMA_WADDR_WSRC_ADDR__##e)
#define BFM_SYDMA_WADDR_WSRC_ADDR_V(v)  BM_SYDMA_WADDR_WSRC_ADDR

#define HW_SYDMA_XFER_COUNT             HW(SYDMA_XFER_COUNT)
#define HWA_SYDMA_XFER_COUNT            (0x80026000 + 0x30)
#define HWT_SYDMA_XFER_COUNT            HWIO_32_RW
#define HWN_SYDMA_XFER_COUNT            SYDMA_XFER_COUNT
#define HWI_SYDMA_XFER_COUNT            
#define BP_SYDMA_XFER_COUNT_SIZE        0
#define BM_SYDMA_XFER_COUNT_SIZE        0xffffffff
#define BF_SYDMA_XFER_COUNT_SIZE(v)     (((v) & 0xffffffff) << 0)
#define BFM_SYDMA_XFER_COUNT_SIZE(v)    BM_SYDMA_XFER_COUNT_SIZE
#define BF_SYDMA_XFER_COUNT_SIZE_V(e)   BF_SYDMA_XFER_COUNT_SIZE(BV_SYDMA_XFER_COUNT_SIZE__##e)
#define BFM_SYDMA_XFER_COUNT_SIZE_V(v)  BM_SYDMA_XFER_COUNT_SIZE

#define HW_SYDMA_BURST              HW(SYDMA_BURST)
#define HWA_SYDMA_BURST             (0x80026000 + 0x40)
#define HWT_SYDMA_BURST             HWIO_32_RW
#define HWN_SYDMA_BURST             SYDMA_BURST
#define HWI_SYDMA_BURST             
#define BP_SYDMA_BURST_RSVD0        4
#define BM_SYDMA_BURST_RSVD0        0xfffffff0
#define BF_SYDMA_BURST_RSVD0(v)     (((v) & 0xfffffff) << 4)
#define BFM_SYDMA_BURST_RSVD0(v)    BM_SYDMA_BURST_RSVD0
#define BF_SYDMA_BURST_RSVD0_V(e)   BF_SYDMA_BURST_RSVD0(BV_SYDMA_BURST_RSVD0__##e)
#define BFM_SYDMA_BURST_RSVD0_V(v)  BM_SYDMA_BURST_RSVD0
#define BP_SYDMA_BURST_WLEN         2
#define BM_SYDMA_BURST_WLEN         0xc
#define BV_SYDMA_BURST_WLEN__1      0x0
#define BV_SYDMA_BURST_WLEN__2      0x1
#define BV_SYDMA_BURST_WLEN__4      0x2
#define BV_SYDMA_BURST_WLEN__8      0x3
#define BF_SYDMA_BURST_WLEN(v)      (((v) & 0x3) << 2)
#define BFM_SYDMA_BURST_WLEN(v)     BM_SYDMA_BURST_WLEN
#define BF_SYDMA_BURST_WLEN_V(e)    BF_SYDMA_BURST_WLEN(BV_SYDMA_BURST_WLEN__##e)
#define BFM_SYDMA_BURST_WLEN_V(v)   BM_SYDMA_BURST_WLEN
#define BP_SYDMA_BURST_RLEN         0
#define BM_SYDMA_BURST_RLEN         0x3
#define BV_SYDMA_BURST_RLEN__1      0x0
#define BV_SYDMA_BURST_RLEN__2      0x1
#define BV_SYDMA_BURST_RLEN__4      0x2
#define BV_SYDMA_BURST_RLEN__8      0x3
#define BF_SYDMA_BURST_RLEN(v)      (((v) & 0x3) << 0)
#define BFM_SYDMA_BURST_RLEN(v)     BM_SYDMA_BURST_RLEN
#define BF_SYDMA_BURST_RLEN_V(e)    BF_SYDMA_BURST_RLEN(BV_SYDMA_BURST_RLEN__##e)
#define BFM_SYDMA_BURST_RLEN_V(v)   BM_SYDMA_BURST_RLEN

#define HW_SYDMA_DACK               HW(SYDMA_DACK)
#define HWA_SYDMA_DACK              (0x80026000 + 0x50)
#define HWT_SYDMA_DACK              HWIO_32_RW
#define HWN_SYDMA_DACK              SYDMA_DACK
#define HWI_SYDMA_DACK              
#define BP_SYDMA_DACK_RSVD0         8
#define BM_SYDMA_DACK_RSVD0         0xffffff00
#define BF_SYDMA_DACK_RSVD0(v)      (((v) & 0xffffff) << 8)
#define BFM_SYDMA_DACK_RSVD0(v)     BM_SYDMA_DACK_RSVD0
#define BF_SYDMA_DACK_RSVD0_V(e)    BF_SYDMA_DACK_RSVD0(BV_SYDMA_DACK_RSVD0__##e)
#define BFM_SYDMA_DACK_RSVD0_V(v)   BM_SYDMA_DACK_RSVD0
#define BP_SYDMA_DACK_WDELAY        4
#define BM_SYDMA_DACK_WDELAY        0xf0
#define BF_SYDMA_DACK_WDELAY(v)     (((v) & 0xf) << 4)
#define BFM_SYDMA_DACK_WDELAY(v)    BM_SYDMA_DACK_WDELAY
#define BF_SYDMA_DACK_WDELAY_V(e)   BF_SYDMA_DACK_WDELAY(BV_SYDMA_DACK_WDELAY__##e)
#define BFM_SYDMA_DACK_WDELAY_V(v)  BM_SYDMA_DACK_WDELAY
#define BP_SYDMA_DACK_RDELAY        0
#define BM_SYDMA_DACK_RDELAY        0xf
#define BF_SYDMA_DACK_RDELAY(v)     (((v) & 0xf) << 0)
#define BFM_SYDMA_DACK_RDELAY(v)    BM_SYDMA_DACK_RDELAY
#define BF_SYDMA_DACK_RDELAY_V(e)   BF_SYDMA_DACK_RDELAY(BV_SYDMA_DACK_RDELAY__##e)
#define BFM_SYDMA_DACK_RDELAY_V(v)  BM_SYDMA_DACK_RDELAY

#define HW_SYDMA_DEBUG0             HW(SYDMA_DEBUG0)
#define HWA_SYDMA_DEBUG0            (0x80026000 + 0x100)
#define HWT_SYDMA_DEBUG0            HWIO_32_RW
#define HWN_SYDMA_DEBUG0            SYDMA_DEBUG0
#define HWI_SYDMA_DEBUG0            
#define BP_SYDMA_DEBUG0_DATA        0
#define BM_SYDMA_DEBUG0_DATA        0xffffffff
#define BF_SYDMA_DEBUG0_DATA(v)     (((v) & 0xffffffff) << 0)
#define BFM_SYDMA_DEBUG0_DATA(v)    BM_SYDMA_DEBUG0_DATA
#define BF_SYDMA_DEBUG0_DATA_V(e)   BF_SYDMA_DEBUG0_DATA(BV_SYDMA_DEBUG0_DATA__##e)
#define BFM_SYDMA_DEBUG0_DATA_V(v)  BM_SYDMA_DEBUG0_DATA

#define HW_SYDMA_DEBUG1             HW(SYDMA_DEBUG1)
#define HWA_SYDMA_DEBUG1            (0x80026000 + 0x110)
#define HWT_SYDMA_DEBUG1            HWIO_32_RW
#define HWN_SYDMA_DEBUG1            SYDMA_DEBUG1
#define HWI_SYDMA_DEBUG1            
#define BP_SYDMA_DEBUG1_DATA        0
#define BM_SYDMA_DEBUG1_DATA        0xffffffff
#define BF_SYDMA_DEBUG1_DATA(v)     (((v) & 0xffffffff) << 0)
#define BFM_SYDMA_DEBUG1_DATA(v)    BM_SYDMA_DEBUG1_DATA
#define BF_SYDMA_DEBUG1_DATA_V(e)   BF_SYDMA_DEBUG1_DATA(BV_SYDMA_DEBUG1_DATA__##e)
#define BFM_SYDMA_DEBUG1_DATA_V(v)  BM_SYDMA_DEBUG1_DATA

#define HW_SYDMA_DEBUG2             HW(SYDMA_DEBUG2)
#define HWA_SYDMA_DEBUG2            (0x80026000 + 0x120)
#define HWT_SYDMA_DEBUG2            HWIO_32_RW
#define HWN_SYDMA_DEBUG2            SYDMA_DEBUG2
#define HWI_SYDMA_DEBUG2            
#define BP_SYDMA_DEBUG2_DATA        0
#define BM_SYDMA_DEBUG2_DATA        0xffffffff
#define BF_SYDMA_DEBUG2_DATA(v)     (((v) & 0xffffffff) << 0)
#define BFM_SYDMA_DEBUG2_DATA(v)    BM_SYDMA_DEBUG2_DATA
#define BF_SYDMA_DEBUG2_DATA_V(e)   BF_SYDMA_DEBUG2_DATA(BV_SYDMA_DEBUG2_DATA__##e)
#define BFM_SYDMA_DEBUG2_DATA_V(v)  BM_SYDMA_DEBUG2_DATA

#define HW_SYDMA_VERSION                HW(SYDMA_VERSION)
#define HWA_SYDMA_VERSION               (0x80026000 + 0x130)
#define HWT_SYDMA_VERSION               HWIO_32_RW
#define HWN_SYDMA_VERSION               SYDMA_VERSION
#define HWI_SYDMA_VERSION               
#define BP_SYDMA_VERSION_MAJOR          24
#define BM_SYDMA_VERSION_MAJOR          0xff000000
#define BF_SYDMA_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
#define BFM_SYDMA_VERSION_MAJOR(v)      BM_SYDMA_VERSION_MAJOR
#define BF_SYDMA_VERSION_MAJOR_V(e)     BF_SYDMA_VERSION_MAJOR(BV_SYDMA_VERSION_MAJOR__##e)
#define BFM_SYDMA_VERSION_MAJOR_V(v)    BM_SYDMA_VERSION_MAJOR
#define BP_SYDMA_VERSION_MINOR          16
#define BM_SYDMA_VERSION_MINOR          0xff0000
#define BF_SYDMA_VERSION_MINOR(v)       (((v) & 0xff) << 16)
#define BFM_SYDMA_VERSION_MINOR(v)      BM_SYDMA_VERSION_MINOR
#define BF_SYDMA_VERSION_MINOR_V(e)     BF_SYDMA_VERSION_MINOR(BV_SYDMA_VERSION_MINOR__##e)
#define BFM_SYDMA_VERSION_MINOR_V(v)    BM_SYDMA_VERSION_MINOR
#define BP_SYDMA_VERSION_STEP           0
#define BM_SYDMA_VERSION_STEP           0xffff
#define BF_SYDMA_VERSION_STEP(v)        (((v) & 0xffff) << 0)
#define BFM_SYDMA_VERSION_STEP(v)       BM_SYDMA_VERSION_STEP
#define BF_SYDMA_VERSION_STEP_V(e)      BF_SYDMA_VERSION_STEP(BV_SYDMA_VERSION_STEP__##e)
#define BFM_SYDMA_VERSION_STEP_V(v)     BM_SYDMA_VERSION_STEP

#endif /* __HEADERGEN_IMX233_SYDMA_H__*/
