/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * stmp3600 version: 2.4.0
 * stmp3600 authors: Amaury Pouly
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_STMP3600_POWER_H__
#define __HEADERGEN_STMP3600_POWER_H__

#define HW_POWER_CTRL                               HW(POWER_CTRL)
#define HWA_POWER_CTRL                              (0x80044000 + 0x0)
#define HWT_POWER_CTRL                              HWIO_32_RW
#define HWN_POWER_CTRL                              POWER_CTRL
#define HWI_POWER_CTRL                              
#define HW_POWER_CTRL_SET                           HW(POWER_CTRL_SET)
#define HWA_POWER_CTRL_SET                          (HWA_POWER_CTRL + 0x4)
#define HWT_POWER_CTRL_SET                          HWIO_32_WO
#define HWN_POWER_CTRL_SET                          POWER_CTRL
#define HWI_POWER_CTRL_SET                          
#define HW_POWER_CTRL_CLR                           HW(POWER_CTRL_CLR)
#define HWA_POWER_CTRL_CLR                          (HWA_POWER_CTRL + 0x8)
#define HWT_POWER_CTRL_CLR                          HWIO_32_WO
#define HWN_POWER_CTRL_CLR                          POWER_CTRL
#define HWI_POWER_CTRL_CLR                          
#define HW_POWER_CTRL_TOG                           HW(POWER_CTRL_TOG)
#define HWA_POWER_CTRL_TOG                          (HWA_POWER_CTRL + 0xc)
#define HWT_POWER_CTRL_TOG                          HWIO_32_WO
#define HWN_POWER_CTRL_TOG                          POWER_CTRL
#define HWI_POWER_CTRL_TOG                          
#define BP_POWER_CTRL_CLKGATE                       30
#define BM_POWER_CTRL_CLKGATE                       0x40000000
#define BF_POWER_CTRL_CLKGATE(v)                    (((v) & 0x1) << 30)
#define BFM_POWER_CTRL_CLKGATE(v)                   BM_POWER_CTRL_CLKGATE
#define BF_POWER_CTRL_CLKGATE_V(e)                  BF_POWER_CTRL_CLKGATE(BV_POWER_CTRL_CLKGATE__##e)
#define BFM_POWER_CTRL_CLKGATE_V(v)                 BM_POWER_CTRL_CLKGATE
#define BP_POWER_CTRL_BATT_BO_IRQ                   8
#define BM_POWER_CTRL_BATT_BO_IRQ                   0x100
#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) & 0x1) << 8)
#define BFM_POWER_CTRL_BATT_BO_IRQ(v)               BM_POWER_CTRL_BATT_BO_IRQ
#define BF_POWER_CTRL_BATT_BO_IRQ_V(e)              BF_POWER_CTRL_BATT_BO_IRQ(BV_POWER_CTRL_BATT_BO_IRQ__##e)
#define BFM_POWER_CTRL_BATT_BO_IRQ_V(v)             BM_POWER_CTRL_BATT_BO_IRQ
#define BP_POWER_CTRL_ENIRQBATT_BO                  7
#define BM_POWER_CTRL_ENIRQBATT_BO                  0x80
#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) & 0x1) << 7)
#define BFM_POWER_CTRL_ENIRQBATT_BO(v)              BM_POWER_CTRL_ENIRQBATT_BO
#define BF_POWER_CTRL_ENIRQBATT_BO_V(e)             BF_POWER_CTRL_ENIRQBATT_BO(BV_POWER_CTRL_ENIRQBATT_BO__##e)
#define BFM_POWER_CTRL_ENIRQBATT_BO_V(v)            BM_POWER_CTRL_ENIRQBATT_BO
#define BP_POWER_CTRL_VDDIO_BO_IRQ                  6
#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x40
#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) & 0x1) << 6)
#define BFM_POWER_CTRL_VDDIO_BO_IRQ(v)              BM_POWER_CTRL_VDDIO_BO_IRQ
#define BF_POWER_CTRL_VDDIO_BO_IRQ_V(e)             BF_POWER_CTRL_VDDIO_BO_IRQ(BV_POWER_CTRL_VDDIO_BO_IRQ__##e)
#define BFM_POWER_CTRL_VDDIO_BO_IRQ_V(v)            BM_POWER_CTRL_VDDIO_BO_IRQ
#define BP_POWER_CTRL_ENIRQVDDIO_BO                 5
#define BM_POWER_CTRL_ENIRQVDDIO_BO                 0x20
#define BF_POWER_CTRL_ENIRQVDDIO_BO(v)              (((v) & 0x1) << 5)
#define BFM_POWER_CTRL_ENIRQVDDIO_BO(v)             BM_POWER_CTRL_ENIRQVDDIO_BO
#define BF_POWER_CTRL_ENIRQVDDIO_BO_V(e)            BF_POWER_CTRL_ENIRQVDDIO_BO(BV_POWER_CTRL_ENIRQVDDIO_BO__##e)
#define BFM_POWER_CTRL_ENIRQVDDIO_BO_V(v)           BM_POWER_CTRL_ENIRQVDDIO_BO
#define BP_POWER_CTRL_VDDD_BO_IRQ                   4
#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x10
#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) & 0x1) << 4)
#define BFM_POWER_CTRL_VDDD_BO_IRQ(v)               BM_POWER_CTRL_VDDD_BO_IRQ
#define BF_POWER_CTRL_VDDD_BO_IRQ_V(e)              BF_POWER_CTRL_VDDD_BO_IRQ(BV_POWER_CTRL_VDDD_BO_IRQ__##e)
#define BFM_POWER_CTRL_VDDD_BO_IRQ_V(v)             BM_POWER_CTRL_VDDD_BO_IRQ
#define BP_POWER_CTRL_ENIRQVDDD_BO                  3
#define BM_POWER_CTRL_ENIRQVDDD_BO                  0x8
#define BF_POWER_CTRL_ENIRQVDDD_BO(v)               (((v) & 0x1) << 3)
#define BFM_POWER_CTRL_ENIRQVDDD_BO(v)              BM_POWER_CTRL_ENIRQVDDD_BO
#define BF_POWER_CTRL_ENIRQVDDD_BO_V(e)             BF_POWER_CTRL_ENIRQVDDD_BO(BV_POWER_CTRL_ENIRQVDDD_BO__##e)
#define BFM_POWER_CTRL_ENIRQVDDD_BO_V(v)            BM_POWER_CTRL_ENIRQVDDD_BO
#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) & 0x1) << 2)
#define BFM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)   BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO
#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO_V(e)  BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(BV_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO__##e)
#define BFM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO_V(v) BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO
#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) & 0x1) << 1)
#define BFM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)        BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ
#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ_V(e)       BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(BV_POWER_CTRL_VDD5V_GT_VDDIO_IRQ__##e)
#define BFM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ_V(v)      BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ
#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) & 0x1) << 0)
#define BFM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)      BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO
#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO_V(e)     BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(BV_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO__##e)
#define BFM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO_V(v)    BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO

#define HW_POWER_5VCTRL                             HW(POWER_5VCTRL)
#define HWA_POWER_5VCTRL                            (0x80044000 + 0x10)
#define HWT_POWER_5VCTRL                            HWIO_32_RW
#define HWN_POWER_5VCTRL                            POWER_5VCTRL
#define HWI_POWER_5VCTRL                            
#define HW_POWER_5VCTRL_SET                         HW(POWER_5VCTRL_SET)
#define HWA_POWER_5VCTRL_SET                        (HWA_POWER_5VCTRL + 0x4)
#define HWT_POWER_5VCTRL_SET                        HWIO_32_WO
#define HWN_POWER_5VCTRL_SET                        POWER_5VCTRL
#define HWI_POWER_5VCTRL_SET                        
#define HW_POWER_5VCTRL_CLR                         HW(POWER_5VCTRL_CLR)
#define HWA_POWER_5VCTRL_CLR                        (HWA_POWER_5VCTRL + 0x8)
#define HWT_POWER_5VCTRL_CLR                        HWIO_32_WO
#define HWN_POWER_5VCTRL_CLR                        POWER_5VCTRL
#define HWI_POWER_5VCTRL_CLR                        
#define HW_POWER_5VCTRL_TOG                         HW(POWER_5VCTRL_TOG)
#define HWA_POWER_5VCTRL_TOG                        (HWA_POWER_5VCTRL + 0xc)
#define HWT_POWER_5VCTRL_TOG                        HWIO_32_WO
#define HWN_POWER_5VCTRL_TOG                        POWER_5VCTRL
#define HWI_POWER_5VCTRL_TOG                        
#define BP_POWER_5VCTRL_PWDN_5VBRNOUT               21
#define BM_POWER_5VCTRL_PWDN_5VBRNOUT               0x200000
#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)            (((v) & 0x1) << 21)
#define BFM_POWER_5VCTRL_PWDN_5VBRNOUT(v)           BM_POWER_5VCTRL_PWDN_5VBRNOUT
#define BF_POWER_5VCTRL_PWDN_5VBRNOUT_V(e)          BF_POWER_5VCTRL_PWDN_5VBRNOUT(BV_POWER_5VCTRL_PWDN_5VBRNOUT__##e)
#define BFM_POWER_5VCTRL_PWDN_5VBRNOUT_V(v)         BM_POWER_5VCTRL_PWDN_5VBRNOUT
#define BP_POWER_5VCTRL_PWDN_IOBRNOUT               20
#define BM_POWER_5VCTRL_PWDN_IOBRNOUT               0x100000
#define BF_POWER_5VCTRL_PWDN_IOBRNOUT(v)            (((v) & 0x1) << 20)
#define BFM_POWER_5VCTRL_PWDN_IOBRNOUT(v)           BM_POWER_5VCTRL_PWDN_IOBRNOUT
#define BF_POWER_5VCTRL_PWDN_IOBRNOUT_V(e)          BF_POWER_5VCTRL_PWDN_IOBRNOUT(BV_POWER_5VCTRL_PWDN_IOBRNOUT__##e)
#define BFM_POWER_5VCTRL_PWDN_IOBRNOUT_V(v)         BM_POWER_5VCTRL_PWDN_IOBRNOUT
#define BP_POWER_5VCTRL_DISABLE_ILIMIT              19
#define BM_POWER_5VCTRL_DISABLE_ILIMIT              0x80000
#define BF_POWER_5VCTRL_DISABLE_ILIMIT(v)           (((v) & 0x1) << 19)
#define BFM_POWER_5VCTRL_DISABLE_ILIMIT(v)          BM_POWER_5VCTRL_DISABLE_ILIMIT
#define BF_POWER_5VCTRL_DISABLE_ILIMIT_V(e)         BF_POWER_5VCTRL_DISABLE_ILIMIT(BV_POWER_5VCTRL_DISABLE_ILIMIT__##e)
#define BFM_POWER_5VCTRL_DISABLE_ILIMIT_V(v)        BM_POWER_5VCTRL_DISABLE_ILIMIT
#define BP_POWER_5VCTRL_DCDC_XFER                   18
#define BM_POWER_5VCTRL_DCDC_XFER                   0x40000
#define BF_POWER_5VCTRL_DCDC_XFER(v)                (((v) & 0x1) << 18)
#define BFM_POWER_5VCTRL_DCDC_XFER(v)               BM_POWER_5VCTRL_DCDC_XFER
#define BF_POWER_5VCTRL_DCDC_XFER_V(e)              BF_POWER_5VCTRL_DCDC_XFER(BV_POWER_5VCTRL_DCDC_XFER__##e)
#define BFM_POWER_5VCTRL_DCDC_XFER_V(v)             BM_POWER_5VCTRL_DCDC_XFER
#define BP_POWER_5VCTRL_EN_BATT_PULLDN              17
#define BM_POWER_5VCTRL_EN_BATT_PULLDN              0x20000
#define BF_POWER_5VCTRL_EN_BATT_PULLDN(v)           (((v) & 0x1) << 17)
#define BFM_POWER_5VCTRL_EN_BATT_PULLDN(v)          BM_POWER_5VCTRL_EN_BATT_PULLDN
#define BF_POWER_5VCTRL_EN_BATT_PULLDN_V(e)         BF_POWER_5VCTRL_EN_BATT_PULLDN(BV_POWER_5VCTRL_EN_BATT_PULLDN__##e)
#define BFM_POWER_5VCTRL_EN_BATT_PULLDN_V(v)        BM_POWER_5VCTRL_EN_BATT_PULLDN
#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT          16
#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT          0x10000
#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)       (((v) & 0x1) << 16)
#define BFM_POWER_5VCTRL_VBUSVALID_5VDETECT(v)      BM_POWER_5VCTRL_VBUSVALID_5VDETECT
#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT_V(e)     BF_POWER_5VCTRL_VBUSVALID_5VDETECT(BV_POWER_5VCTRL_VBUSVALID_5VDETECT__##e)
#define BFM_POWER_5VCTRL_VBUSVALID_5VDETECT_V(v)    BM_POWER_5VCTRL_VBUSVALID_5VDETECT
#define BP_POWER_5VCTRL_VBUSVALID_TRSH              8
#define BM_POWER_5VCTRL_VBUSVALID_TRSH              0x300
#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)           (((v) & 0x3) << 8)
#define BFM_POWER_5VCTRL_VBUSVALID_TRSH(v)          BM_POWER_5VCTRL_VBUSVALID_TRSH
#define BF_POWER_5VCTRL_VBUSVALID_TRSH_V(e)         BF_POWER_5VCTRL_VBUSVALID_TRSH(BV_POWER_5VCTRL_VBUSVALID_TRSH__##e)
#define BFM_POWER_5VCTRL_VBUSVALID_TRSH_V(v)        BM_POWER_5VCTRL_VBUSVALID_TRSH
#define BP_POWER_5VCTRL_USB_SUSPEND_I               7
#define BM_POWER_5VCTRL_USB_SUSPEND_I               0x80
#define BF_POWER_5VCTRL_USB_SUSPEND_I(v)            (((v) & 0x1) << 7)
#define BFM_POWER_5VCTRL_USB_SUSPEND_I(v)           BM_POWER_5VCTRL_USB_SUSPEND_I
#define BF_POWER_5VCTRL_USB_SUSPEND_I_V(e)          BF_POWER_5VCTRL_USB_SUSPEND_I(BV_POWER_5VCTRL_USB_SUSPEND_I__##e)
#define BFM_POWER_5VCTRL_USB_SUSPEND_I_V(v)         BM_POWER_5VCTRL_USB_SUSPEND_I
#define BP_POWER_5VCTRL_VBUSVALID_TO_B              6
#define BM_POWER_5VCTRL_VBUSVALID_TO_B              0x40
#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)           (((v) & 0x1) << 6)
#define BFM_POWER_5VCTRL_VBUSVALID_TO_B(v)          BM_POWER_5VCTRL_VBUSVALID_TO_B
#define BF_POWER_5VCTRL_VBUSVALID_TO_B_V(e)         BF_POWER_5VCTRL_VBUSVALID_TO_B(BV_POWER_5VCTRL_VBUSVALID_TO_B__##e)
#define BFM_POWER_5VCTRL_VBUSVALID_TO_B_V(v)        BM_POWER_5VCTRL_VBUSVALID_TO_B
#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO              5
#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO              0x20
#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)           (((v) & 0x1) << 5)
#define BFM_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)          BM_POWER_5VCTRL_ILIMIT_EQ_ZERO
#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO_V(e)         BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(BV_POWER_5VCTRL_ILIMIT_EQ_ZERO__##e)
#define BFM_POWER_5VCTRL_ILIMIT_EQ_ZERO_V(v)        BM_POWER_5VCTRL_ILIMIT_EQ_ZERO
#define BP_POWER_5VCTRL_OTG_PWRUP_CMPS              4
#define BM_POWER_5VCTRL_OTG_PWRUP_CMPS              0x10
#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v)           (((v) & 0x1) << 4)
#define BFM_POWER_5VCTRL_OTG_PWRUP_CMPS(v)          BM_POWER_5VCTRL_OTG_PWRUP_CMPS
#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS_V(e)         BF_POWER_5VCTRL_OTG_PWRUP_CMPS(BV_POWER_5VCTRL_OTG_PWRUP_CMPS__##e)
#define BFM_POWER_5VCTRL_OTG_PWRUP_CMPS_V(v)        BM_POWER_5VCTRL_OTG_PWRUP_CMPS
#define BP_POWER_5VCTRL_EN_DCDC2                    3
#define BM_POWER_5VCTRL_EN_DCDC2                    0x8
#define BF_POWER_5VCTRL_EN_DCDC2(v)                 (((v) & 0x1) << 3)
#define BFM_POWER_5VCTRL_EN_DCDC2(v)                BM_POWER_5VCTRL_EN_DCDC2
#define BF_POWER_5VCTRL_EN_DCDC2_V(e)               BF_POWER_5VCTRL_EN_DCDC2(BV_POWER_5VCTRL_EN_DCDC2__##e)
#define BFM_POWER_5VCTRL_EN_DCDC2_V(v)              BM_POWER_5VCTRL_EN_DCDC2
#define BP_POWER_5VCTRL_PWD_VDDD_LINREG             2
#define BM_POWER_5VCTRL_PWD_VDDD_LINREG             0x4
#define BF_POWER_5VCTRL_PWD_VDDD_LINREG(v)          (((v) & 0x1) << 2)
#define BFM_POWER_5VCTRL_PWD_VDDD_LINREG(v)         BM_POWER_5VCTRL_PWD_VDDD_LINREG
#define BF_POWER_5VCTRL_PWD_VDDD_LINREG_V(e)        BF_POWER_5VCTRL_PWD_VDDD_LINREG(BV_POWER_5VCTRL_PWD_VDDD_LINREG__##e)
#define BFM_POWER_5VCTRL_PWD_VDDD_LINREG_V(v)       BM_POWER_5VCTRL_PWD_VDDD_LINREG
#define BP_POWER_5VCTRL_EN_DCDC1                    1
#define BM_POWER_5VCTRL_EN_DCDC1                    0x2
#define BF_POWER_5VCTRL_EN_DCDC1(v)                 (((v) & 0x1) << 1)
#define BFM_POWER_5VCTRL_EN_DCDC1(v)                BM_POWER_5VCTRL_EN_DCDC1
#define BF_POWER_5VCTRL_EN_DCDC1_V(e)               BF_POWER_5VCTRL_EN_DCDC1(BV_POWER_5VCTRL_EN_DCDC1__##e)
#define BFM_POWER_5VCTRL_EN_DCDC1_V(v)              BM_POWER_5VCTRL_EN_DCDC1
#define BP_POWER_5VCTRL_LINREG_OFFSET               0
#define BM_POWER_5VCTRL_LINREG_OFFSET               0x1
#define BF_POWER_5VCTRL_LINREG_OFFSET(v)            (((v) & 0x1) << 0)
#define BFM_POWER_5VCTRL_LINREG_OFFSET(v)           BM_POWER_5VCTRL_LINREG_OFFSET
#define BF_POWER_5VCTRL_LINREG_OFFSET_V(e)          BF_POWER_5VCTRL_LINREG_OFFSET(BV_POWER_5VCTRL_LINREG_OFFSET__##e)
#define BFM_POWER_5VCTRL_LINREG_OFFSET_V(v)         BM_POWER_5VCTRL_LINREG_OFFSET

#define HW_POWER_MINPWR                         HW(POWER_MINPWR)
#define HWA_POWER_MINPWR                        (0x80044000 + 0x20)
#define HWT_POWER_MINPWR                        HWIO_32_RW
#define HWN_POWER_MINPWR                        POWER_MINPWR
#define HWI_POWER_MINPWR                        
#define HW_POWER_MINPWR_SET                     HW(POWER_MINPWR_SET)
#define HWA_POWER_MINPWR_SET                    (HWA_POWER_MINPWR + 0x4)
#define HWT_POWER_MINPWR_SET                    HWIO_32_WO
#define HWN_POWER_MINPWR_SET                    POWER_MINPWR
#define HWI_POWER_MINPWR_SET                    
#define HW_POWER_MINPWR_CLR                     HW(POWER_MINPWR_CLR)
#define HWA_POWER_MINPWR_CLR                    (HWA_POWER_MINPWR + 0x8)
#define HWT_POWER_MINPWR_CLR                    HWIO_32_WO
#define HWN_POWER_MINPWR_CLR                    POWER_MINPWR
#define HWI_POWER_MINPWR_CLR                    
#define HW_POWER_MINPWR_TOG                     HW(POWER_MINPWR_TOG)
#define HWA_POWER_MINPWR_TOG                    (HWA_POWER_MINPWR + 0xc)
#define HWT_POWER_MINPWR_TOG                    HWIO_32_WO
#define HWN_POWER_MINPWR_TOG                    POWER_MINPWR
#define HWI_POWER_MINPWR_TOG                    
#define BP_POWER_MINPWR_TEST_DISCHRG_VBUS       23
#define BM_POWER_MINPWR_TEST_DISCHRG_VBUS       0x800000
#define BF_POWER_MINPWR_TEST_DISCHRG_VBUS(v)    (((v) & 0x1) << 23)
#define BFM_POWER_MINPWR_TEST_DISCHRG_VBUS(v)   BM_POWER_MINPWR_TEST_DISCHRG_VBUS
#define BF_POWER_MINPWR_TEST_DISCHRG_VBUS_V(e)  BF_POWER_MINPWR_TEST_DISCHRG_VBUS(BV_POWER_MINPWR_TEST_DISCHRG_VBUS__##e)
#define BFM_POWER_MINPWR_TEST_DISCHRG_VBUS_V(v) BM_POWER_MINPWR_TEST_DISCHRG_VBUS
#define BP_POWER_MINPWR_TEST_CHRG_VBUS          22
#define BM_POWER_MINPWR_TEST_CHRG_VBUS          0x400000
#define BF_POWER_MINPWR_TEST_CHRG_VBUS(v)       (((v) & 0x1) << 22)
#define BFM_POWER_MINPWR_TEST_CHRG_VBUS(v)      BM_POWER_MINPWR_TEST_CHRG_VBUS
#define BF_POWER_MINPWR_TEST_CHRG_VBUS_V(e)     BF_POWER_MINPWR_TEST_CHRG_VBUS(BV_POWER_MINPWR_TEST_CHRG_VBUS__##e)
#define BFM_POWER_MINPWR_TEST_CHRG_VBUS_V(v)    BM_POWER_MINPWR_TEST_CHRG_VBUS
#define BP_POWER_MINPWR_DC2_TST                 21
#define BM_POWER_MINPWR_DC2_TST                 0x200000
#define BF_POWER_MINPWR_DC2_TST(v)              (((v) & 0x1) << 21)
#define BFM_POWER_MINPWR_DC2_TST(v)             BM_POWER_MINPWR_DC2_TST
#define BF_POWER_MINPWR_DC2_TST_V(e)            BF_POWER_MINPWR_DC2_TST(BV_POWER_MINPWR_DC2_TST__##e)
#define BFM_POWER_MINPWR_DC2_TST_V(v)           BM_POWER_MINPWR_DC2_TST
#define BP_POWER_MINPWR_DC1_TST                 20
#define BM_POWER_MINPWR_DC1_TST                 0x100000
#define BF_POWER_MINPWR_DC1_TST(v)              (((v) & 0x1) << 20)
#define BFM_POWER_MINPWR_DC1_TST(v)             BM_POWER_MINPWR_DC1_TST
#define BF_POWER_MINPWR_DC1_TST_V(e)            BF_POWER_MINPWR_DC1_TST(BV_POWER_MINPWR_DC1_TST__##e)
#define BFM_POWER_MINPWR_DC1_TST_V(v)           BM_POWER_MINPWR_DC1_TST
#define BP_POWER_MINPWR_PERIPHERALSWOFF         19
#define BM_POWER_MINPWR_PERIPHERALSWOFF         0x80000
#define BF_POWER_MINPWR_PERIPHERALSWOFF(v)      (((v) & 0x1) << 19)
#define BFM_POWER_MINPWR_PERIPHERALSWOFF(v)     BM_POWER_MINPWR_PERIPHERALSWOFF
#define BF_POWER_MINPWR_PERIPHERALSWOFF_V(e)    BF_POWER_MINPWR_PERIPHERALSWOFF(BV_POWER_MINPWR_PERIPHERALSWOFF__##e)
#define BFM_POWER_MINPWR_PERIPHERALSWOFF_V(v)   BM_POWER_MINPWR_PERIPHERALSWOFF
#define BP_POWER_MINPWR_TOGGLE_DIF              18
#define BM_POWER_MINPWR_TOGGLE_DIF              0x40000
#define BF_POWER_MINPWR_TOGGLE_DIF(v)           (((v) & 0x1) << 18)
#define BFM_POWER_MINPWR_TOGGLE_DIF(v)          BM_POWER_MINPWR_TOGGLE_DIF
#define BF_POWER_MINPWR_TOGGLE_DIF_V(e)         BF_POWER_MINPWR_TOGGLE_DIF(BV_POWER_MINPWR_TOGGLE_DIF__##e)
#define BFM_POWER_MINPWR_TOGGLE_DIF_V(v)        BM_POWER_MINPWR_TOGGLE_DIF
#define BP_POWER_MINPWR_DISABLE_VDDIOSTEP       17
#define BM_POWER_MINPWR_DISABLE_VDDIOSTEP       0x20000
#define BF_POWER_MINPWR_DISABLE_VDDIOSTEP(v)    (((v) & 0x1) << 17)
#define BFM_POWER_MINPWR_DISABLE_VDDIOSTEP(v)   BM_POWER_MINPWR_DISABLE_VDDIOSTEP
#define BF_POWER_MINPWR_DISABLE_VDDIOSTEP_V(e)  BF_POWER_MINPWR_DISABLE_VDDIOSTEP(BV_POWER_MINPWR_DISABLE_VDDIOSTEP__##e)
#define BFM_POWER_MINPWR_DISABLE_VDDIOSTEP_V(v) BM_POWER_MINPWR_DISABLE_VDDIOSTEP
#define BP_POWER_MINPWR_DISABLE_VDDSTEP         16
#define BM_POWER_MINPWR_DISABLE_VDDSTEP         0x10000
#define BF_POWER_MINPWR_DISABLE_VDDSTEP(v)      (((v) & 0x1) << 16)
#define BFM_POWER_MINPWR_DISABLE_VDDSTEP(v)     BM_POWER_MINPWR_DISABLE_VDDSTEP
#define BF_POWER_MINPWR_DISABLE_VDDSTEP_V(e)    BF_POWER_MINPWR_DISABLE_VDDSTEP(BV_POWER_MINPWR_DISABLE_VDDSTEP__##e)
#define BFM_POWER_MINPWR_DISABLE_VDDSTEP_V(v)   BM_POWER_MINPWR_DISABLE_VDDSTEP
#define BP_POWER_MINPWR_SEL_PLLDIV16CLK         9
#define BM_POWER_MINPWR_SEL_PLLDIV16CLK         0x200
#define BF_POWER_MINPWR_SEL_PLLDIV16CLK(v)      (((v) & 0x1) << 9)
#define BFM_POWER_MINPWR_SEL_PLLDIV16CLK(v)     BM_POWER_MINPWR_SEL_PLLDIV16CLK
#define BF_POWER_MINPWR_SEL_PLLDIV16CLK_V(e)    BF_POWER_MINPWR_SEL_PLLDIV16CLK(BV_POWER_MINPWR_SEL_PLLDIV16CLK__##e)
#define BFM_POWER_MINPWR_SEL_PLLDIV16CLK_V(v)   BM_POWER_MINPWR_SEL_PLLDIV16CLK
#define BP_POWER_MINPWR_PWD_VDDIOBO             8
#define BM_POWER_MINPWR_PWD_VDDIOBO             0x100
#define BF_POWER_MINPWR_PWD_VDDIOBO(v)          (((v) & 0x1) << 8)
#define BFM_POWER_MINPWR_PWD_VDDIOBO(v)         BM_POWER_MINPWR_PWD_VDDIOBO
#define BF_POWER_MINPWR_PWD_VDDIOBO_V(e)        BF_POWER_MINPWR_PWD_VDDIOBO(BV_POWER_MINPWR_PWD_VDDIOBO__##e)
#define BFM_POWER_MINPWR_PWD_VDDIOBO_V(v)       BM_POWER_MINPWR_PWD_VDDIOBO
#define BP_POWER_MINPWR_LESSANA_I               7
#define BM_POWER_MINPWR_LESSANA_I               0x80
#define BF_POWER_MINPWR_LESSANA_I(v)            (((v) & 0x1) << 7)
#define BFM_POWER_MINPWR_LESSANA_I(v)           BM_POWER_MINPWR_LESSANA_I
#define BF_POWER_MINPWR_LESSANA_I_V(e)          BF_POWER_MINPWR_LESSANA_I(BV_POWER_MINPWR_LESSANA_I__##e)
#define BFM_POWER_MINPWR_LESSANA_I_V(v)         BM_POWER_MINPWR_LESSANA_I
#define BP_POWER_MINPWR_DC1_HALFFETS            6
#define BM_POWER_MINPWR_DC1_HALFFETS            0x40
#define BF_POWER_MINPWR_DC1_HALFFETS(v)         (((v) & 0x1) << 6)
#define BFM_POWER_MINPWR_DC1_HALFFETS(v)        BM_POWER_MINPWR_DC1_HALFFETS
#define BF_POWER_MINPWR_DC1_HALFFETS_V(e)       BF_POWER_MINPWR_DC1_HALFFETS(BV_POWER_MINPWR_DC1_HALFFETS__##e)
#define BFM_POWER_MINPWR_DC1_HALFFETS_V(v)      BM_POWER_MINPWR_DC1_HALFFETS
#define BP_POWER_MINPWR_DC2_STOPCLK             5
#define BM_POWER_MINPWR_DC2_STOPCLK             0x20
#define BF_POWER_MINPWR_DC2_STOPCLK(v)          (((v) & 0x1) << 5)
#define BFM_POWER_MINPWR_DC2_STOPCLK(v)         BM_POWER_MINPWR_DC2_STOPCLK
#define BF_POWER_MINPWR_DC2_STOPCLK_V(e)        BF_POWER_MINPWR_DC2_STOPCLK(BV_POWER_MINPWR_DC2_STOPCLK__##e)
#define BFM_POWER_MINPWR_DC2_STOPCLK_V(v)       BM_POWER_MINPWR_DC2_STOPCLK
#define BP_POWER_MINPWR_DC1_STOPCLK             4
#define BM_POWER_MINPWR_DC1_STOPCLK             0x10
#define BF_POWER_MINPWR_DC1_STOPCLK(v)          (((v) & 0x1) << 4)
#define BFM_POWER_MINPWR_DC1_STOPCLK(v)         BM_POWER_MINPWR_DC1_STOPCLK
#define BF_POWER_MINPWR_DC1_STOPCLK_V(e)        BF_POWER_MINPWR_DC1_STOPCLK(BV_POWER_MINPWR_DC1_STOPCLK__##e)
#define BFM_POWER_MINPWR_DC1_STOPCLK_V(v)       BM_POWER_MINPWR_DC1_STOPCLK
#define BP_POWER_MINPWR_EN_DC2_PFM              3
#define BM_POWER_MINPWR_EN_DC2_PFM              0x8
#define BF_POWER_MINPWR_EN_DC2_PFM(v)           (((v) & 0x1) << 3)
#define BFM_POWER_MINPWR_EN_DC2_PFM(v)          BM_POWER_MINPWR_EN_DC2_PFM
#define BF_POWER_MINPWR_EN_DC2_PFM_V(e)         BF_POWER_MINPWR_EN_DC2_PFM(BV_POWER_MINPWR_EN_DC2_PFM__##e)
#define BFM_POWER_MINPWR_EN_DC2_PFM_V(v)        BM_POWER_MINPWR_EN_DC2_PFM
#define BP_POWER_MINPWR_EN_DC1_PFM              2
#define BM_POWER_MINPWR_EN_DC1_PFM              0x4
#define BF_POWER_MINPWR_EN_DC1_PFM(v)           (((v) & 0x1) << 2)
#define BFM_POWER_MINPWR_EN_DC1_PFM(v)          BM_POWER_MINPWR_EN_DC1_PFM
#define BF_POWER_MINPWR_EN_DC1_PFM_V(e)         BF_POWER_MINPWR_EN_DC1_PFM(BV_POWER_MINPWR_EN_DC1_PFM__##e)
#define BFM_POWER_MINPWR_EN_DC1_PFM_V(v)        BM_POWER_MINPWR_EN_DC1_PFM
#define BP_POWER_MINPWR_DC2_HALFCLK             1
#define BM_POWER_MINPWR_DC2_HALFCLK             0x2
#define BF_POWER_MINPWR_DC2_HALFCLK(v)          (((v) & 0x1) << 1)
#define BFM_POWER_MINPWR_DC2_HALFCLK(v)         BM_POWER_MINPWR_DC2_HALFCLK
#define BF_POWER_MINPWR_DC2_HALFCLK_V(e)        BF_POWER_MINPWR_DC2_HALFCLK(BV_POWER_MINPWR_DC2_HALFCLK__##e)
#define BFM_POWER_MINPWR_DC2_HALFCLK_V(v)       BM_POWER_MINPWR_DC2_HALFCLK
#define BP_POWER_MINPWR_DC1_HALFCLK             0
#define BM_POWER_MINPWR_DC1_HALFCLK             0x1
#define BF_POWER_MINPWR_DC1_HALFCLK(v)          (((v) & 0x1) << 0)
#define BFM_POWER_MINPWR_DC1_HALFCLK(v)         BM_POWER_MINPWR_DC1_HALFCLK
#define BF_POWER_MINPWR_DC1_HALFCLK_V(e)        BF_POWER_MINPWR_DC1_HALFCLK(BV_POWER_MINPWR_DC1_HALFCLK__##e)
#define BFM_POWER_MINPWR_DC1_HALFCLK_V(v)       BM_POWER_MINPWR_DC1_HALFCLK

#define HW_POWER_BATTCHRG                       HW(POWER_BATTCHRG)
#define HWA_POWER_BATTCHRG                      (0x80044000 + 0x30)
#define HWT_POWER_BATTCHRG                      HWIO_32_RW
#define HWN_POWER_BATTCHRG                      POWER_BATTCHRG
#define HWI_POWER_BATTCHRG                      
#define HW_POWER_BATTCHRG_SET                   HW(POWER_BATTCHRG_SET)
#define HWA_POWER_BATTCHRG_SET                  (HWA_POWER_BATTCHRG + 0x4)
#define HWT_POWER_BATTCHRG_SET                  HWIO_32_WO
#define HWN_POWER_BATTCHRG_SET                  POWER_BATTCHRG
#define HWI_POWER_BATTCHRG_SET                  
#define HW_POWER_BATTCHRG_CLR                   HW(POWER_BATTCHRG_CLR)
#define HWA_POWER_BATTCHRG_CLR                  (HWA_POWER_BATTCHRG + 0x8)
#define HWT_POWER_BATTCHRG_CLR                  HWIO_32_WO
#define HWN_POWER_BATTCHRG_CLR                  POWER_BATTCHRG
#define HWI_POWER_BATTCHRG_CLR                  
#define HW_POWER_BATTCHRG_TOG                   HW(POWER_BATTCHRG_TOG)
#define HWA_POWER_BATTCHRG_TOG                  (HWA_POWER_BATTCHRG + 0xc)
#define HWT_POWER_BATTCHRG_TOG                  HWIO_32_WO
#define HWN_POWER_BATTCHRG_TOG                  POWER_BATTCHRG
#define HWI_POWER_BATTCHRG_TOG                  
#define BP_POWER_BATTCHRG_CHRG_STS_OFF          19
#define BM_POWER_BATTCHRG_CHRG_STS_OFF          0x80000
#define BF_POWER_BATTCHRG_CHRG_STS_OFF(v)       (((v) & 0x1) << 19)
#define BFM_POWER_BATTCHRG_CHRG_STS_OFF(v)      BM_POWER_BATTCHRG_CHRG_STS_OFF
#define BF_POWER_BATTCHRG_CHRG_STS_OFF_V(e)     BF_POWER_BATTCHRG_CHRG_STS_OFF(BV_POWER_BATTCHRG_CHRG_STS_OFF__##e)
#define BFM_POWER_BATTCHRG_CHRG_STS_OFF_V(v)    BM_POWER_BATTCHRG_CHRG_STS_OFF
#define BP_POWER_BATTCHRG_LIION_4P1             18
#define BM_POWER_BATTCHRG_LIION_4P1             0x40000
#define BF_POWER_BATTCHRG_LIION_4P1(v)          (((v) & 0x1) << 18)
#define BFM_POWER_BATTCHRG_LIION_4P1(v)         BM_POWER_BATTCHRG_LIION_4P1
#define BF_POWER_BATTCHRG_LIION_4P1_V(e)        BF_POWER_BATTCHRG_LIION_4P1(BV_POWER_BATTCHRG_LIION_4P1__##e)
#define BFM_POWER_BATTCHRG_LIION_4P1_V(v)       BM_POWER_BATTCHRG_LIION_4P1
#define BP_POWER_BATTCHRG_USE_EXTERN_R          17
#define BM_POWER_BATTCHRG_USE_EXTERN_R          0x20000
#define BF_POWER_BATTCHRG_USE_EXTERN_R(v)       (((v) & 0x1) << 17)
#define BFM_POWER_BATTCHRG_USE_EXTERN_R(v)      BM_POWER_BATTCHRG_USE_EXTERN_R
#define BF_POWER_BATTCHRG_USE_EXTERN_R_V(e)     BF_POWER_BATTCHRG_USE_EXTERN_R(BV_POWER_BATTCHRG_USE_EXTERN_R__##e)
#define BFM_POWER_BATTCHRG_USE_EXTERN_R_V(v)    BM_POWER_BATTCHRG_USE_EXTERN_R
#define BP_POWER_BATTCHRG_PWD_BATTCHRG          16
#define BM_POWER_BATTCHRG_PWD_BATTCHRG          0x10000
#define BF_POWER_BATTCHRG_PWD_BATTCHRG(v)       (((v) & 0x1) << 16)
#define BFM_POWER_BATTCHRG_PWD_BATTCHRG(v)      BM_POWER_BATTCHRG_PWD_BATTCHRG
#define BF_POWER_BATTCHRG_PWD_BATTCHRG_V(e)     BF_POWER_BATTCHRG_PWD_BATTCHRG(BV_POWER_BATTCHRG_PWD_BATTCHRG__##e)
#define BFM_POWER_BATTCHRG_PWD_BATTCHRG_V(v)    BM_POWER_BATTCHRG_PWD_BATTCHRG
#define BP_POWER_BATTCHRG_STOP_ILIMIT           8
#define BM_POWER_BATTCHRG_STOP_ILIMIT           0xf00
#define BF_POWER_BATTCHRG_STOP_ILIMIT(v)        (((v) & 0xf) << 8)
#define BFM_POWER_BATTCHRG_STOP_ILIMIT(v)       BM_POWER_BATTCHRG_STOP_ILIMIT
#define BF_POWER_BATTCHRG_STOP_ILIMIT_V(e)      BF_POWER_BATTCHRG_STOP_ILIMIT(BV_POWER_BATTCHRG_STOP_ILIMIT__##e)
#define BFM_POWER_BATTCHRG_STOP_ILIMIT_V(v)     BM_POWER_BATTCHRG_STOP_ILIMIT
#define BP_POWER_BATTCHRG_BATTCHRG_I            0
#define BM_POWER_BATTCHRG_BATTCHRG_I            0x3f
#define BF_POWER_BATTCHRG_BATTCHRG_I(v)         (((v) & 0x3f) << 0)
#define BFM_POWER_BATTCHRG_BATTCHRG_I(v)        BM_POWER_BATTCHRG_BATTCHRG_I
#define BF_POWER_BATTCHRG_BATTCHRG_I_V(e)       BF_POWER_BATTCHRG_BATTCHRG_I(BV_POWER_BATTCHRG_BATTCHRG_I__##e)
#define BFM_POWER_BATTCHRG_BATTCHRG_I_V(v)      BM_POWER_BATTCHRG_BATTCHRG_I

#define HW_POWER_VDDCTRL                    HW(POWER_VDDCTRL)
#define HWA_POWER_VDDCTRL                   (0x80044000 + 0x40)
#define HWT_POWER_VDDCTRL                   HWIO_32_RW
#define HWN_POWER_VDDCTRL                   POWER_VDDCTRL
#define HWI_POWER_VDDCTRL                   
#define BP_POWER_VDDCTRL_VDDIO_BO           24
#define BM_POWER_VDDCTRL_VDDIO_BO           0x1f000000
#define BF_POWER_VDDCTRL_VDDIO_BO(v)        (((v) & 0x1f) << 24)
#define BFM_POWER_VDDCTRL_VDDIO_BO(v)       BM_POWER_VDDCTRL_VDDIO_BO
#define BF_POWER_VDDCTRL_VDDIO_BO_V(e)      BF_POWER_VDDCTRL_VDDIO_BO(BV_POWER_VDDCTRL_VDDIO_BO__##e)
#define BFM_POWER_VDDCTRL_VDDIO_BO_V(v)     BM_POWER_VDDCTRL_VDDIO_BO
#define BP_POWER_VDDCTRL_VDDIO_TRG          16
#define BM_POWER_VDDCTRL_VDDIO_TRG          0x1f0000
#define BF_POWER_VDDCTRL_VDDIO_TRG(v)       (((v) & 0x1f) << 16)
#define BFM_POWER_VDDCTRL_VDDIO_TRG(v)      BM_POWER_VDDCTRL_VDDIO_TRG
#define BF_POWER_VDDCTRL_VDDIO_TRG_V(e)     BF_POWER_VDDCTRL_VDDIO_TRG(BV_POWER_VDDCTRL_VDDIO_TRG__##e)
#define BFM_POWER_VDDCTRL_VDDIO_TRG_V(v)    BM_POWER_VDDCTRL_VDDIO_TRG
#define BP_POWER_VDDCTRL_VDDD_BO            8
#define BM_POWER_VDDCTRL_VDDD_BO            0x1f00
#define BF_POWER_VDDCTRL_VDDD_BO(v)         (((v) & 0x1f) << 8)
#define BFM_POWER_VDDCTRL_VDDD_BO(v)        BM_POWER_VDDCTRL_VDDD_BO
#define BF_POWER_VDDCTRL_VDDD_BO_V(e)       BF_POWER_VDDCTRL_VDDD_BO(BV_POWER_VDDCTRL_VDDD_BO__##e)
#define BFM_POWER_VDDCTRL_VDDD_BO_V(v)      BM_POWER_VDDCTRL_VDDD_BO
#define BP_POWER_VDDCTRL_VDDD_TRG           0
#define BM_POWER_VDDCTRL_VDDD_TRG           0x1f
#define BF_POWER_VDDCTRL_VDDD_TRG(v)        (((v) & 0x1f) << 0)
#define BFM_POWER_VDDCTRL_VDDD_TRG(v)       BM_POWER_VDDCTRL_VDDD_TRG
#define BF_POWER_VDDCTRL_VDDD_TRG_V(e)      BF_POWER_VDDCTRL_VDDD_TRG(BV_POWER_VDDCTRL_VDDD_TRG__##e)
#define BFM_POWER_VDDCTRL_VDDD_TRG_V(v)     BM_POWER_VDDCTRL_VDDD_TRG

#define HW_POWER_DC1MULTOUT                 HW(POWER_DC1MULTOUT)
#define HWA_POWER_DC1MULTOUT                (0x80044000 + 0x50)
#define HWT_POWER_DC1MULTOUT                HWIO_32_RW
#define HWN_POWER_DC1MULTOUT                POWER_DC1MULTOUT
#define HWI_POWER_DC1MULTOUT                
#define BP_POWER_DC1MULTOUT_FUNCV           16
#define BM_POWER_DC1MULTOUT_FUNCV           0x1ff0000
#define BF_POWER_DC1MULTOUT_FUNCV(v)        (((v) & 0x1ff) << 16)
#define BFM_POWER_DC1MULTOUT_FUNCV(v)       BM_POWER_DC1MULTOUT_FUNCV
#define BF_POWER_DC1MULTOUT_FUNCV_V(e)      BF_POWER_DC1MULTOUT_FUNCV(BV_POWER_DC1MULTOUT_FUNCV__##e)
#define BFM_POWER_DC1MULTOUT_FUNCV_V(v)     BM_POWER_DC1MULTOUT_FUNCV
#define BP_POWER_DC1MULTOUT_EN_BATADJ       8
#define BM_POWER_DC1MULTOUT_EN_BATADJ       0x100
#define BF_POWER_DC1MULTOUT_EN_BATADJ(v)    (((v) & 0x1) << 8)
#define BFM_POWER_DC1MULTOUT_EN_BATADJ(v)   BM_POWER_DC1MULTOUT_EN_BATADJ
#define BF_POWER_DC1MULTOUT_EN_BATADJ_V(e)  BF_POWER_DC1MULTOUT_EN_BATADJ(BV_POWER_DC1MULTOUT_EN_BATADJ__##e)
#define BFM_POWER_DC1MULTOUT_EN_BATADJ_V(v) BM_POWER_DC1MULTOUT_EN_BATADJ
#define BP_POWER_DC1MULTOUT_ADJTN           0
#define BM_POWER_DC1MULTOUT_ADJTN           0xf
#define BF_POWER_DC1MULTOUT_ADJTN(v)        (((v) & 0xf) << 0)
#define BFM_POWER_DC1MULTOUT_ADJTN(v)       BM_POWER_DC1MULTOUT_ADJTN
#define BF_POWER_DC1MULTOUT_ADJTN_V(e)      BF_POWER_DC1MULTOUT_ADJTN(BV_POWER_DC1MULTOUT_ADJTN__##e)
#define BFM_POWER_DC1MULTOUT_ADJTN_V(v)     BM_POWER_DC1MULTOUT_ADJTN

#define HW_POWER_DC1LIMITS                      HW(POWER_DC1LIMITS)
#define HWA_POWER_DC1LIMITS                     (0x80044000 + 0x60)
#define HWT_POWER_DC1LIMITS                     HWIO_32_RW
#define HWN_POWER_DC1LIMITS                     POWER_DC1LIMITS
#define HWI_POWER_DC1LIMITS                     
#define BP_POWER_DC1LIMITS_EN_PFETOFF           24
#define BM_POWER_DC1LIMITS_EN_PFETOFF           0x1000000
#define BF_POWER_DC1LIMITS_EN_PFETOFF(v)        (((v) & 0x1) << 24)
#define BFM_POWER_DC1LIMITS_EN_PFETOFF(v)       BM_POWER_DC1LIMITS_EN_PFETOFF
#define BF_POWER_DC1LIMITS_EN_PFETOFF_V(e)      BF_POWER_DC1LIMITS_EN_PFETOFF(BV_POWER_DC1LIMITS_EN_PFETOFF__##e)
#define BFM_POWER_DC1LIMITS_EN_PFETOFF_V(v)     BM_POWER_DC1LIMITS_EN_PFETOFF
#define BP_POWER_DC1LIMITS_POSLIMIT_BOOST       16
#define BM_POWER_DC1LIMITS_POSLIMIT_BOOST       0x7f0000
#define BF_POWER_DC1LIMITS_POSLIMIT_BOOST(v)    (((v) & 0x7f) << 16)
#define BFM_POWER_DC1LIMITS_POSLIMIT_BOOST(v)   BM_POWER_DC1LIMITS_POSLIMIT_BOOST
#define BF_POWER_DC1LIMITS_POSLIMIT_BOOST_V(e)  BF_POWER_DC1LIMITS_POSLIMIT_BOOST(BV_POWER_DC1LIMITS_POSLIMIT_BOOST__##e)
#define BFM_POWER_DC1LIMITS_POSLIMIT_BOOST_V(v) BM_POWER_DC1LIMITS_POSLIMIT_BOOST
#define BP_POWER_DC1LIMITS_POSLIMIT_BUCK        8
#define BM_POWER_DC1LIMITS_POSLIMIT_BUCK        0x7f00
#define BF_POWER_DC1LIMITS_POSLIMIT_BUCK(v)     (((v) & 0x7f) << 8)
#define BFM_POWER_DC1LIMITS_POSLIMIT_BUCK(v)    BM_POWER_DC1LIMITS_POSLIMIT_BUCK
#define BF_POWER_DC1LIMITS_POSLIMIT_BUCK_V(e)   BF_POWER_DC1LIMITS_POSLIMIT_BUCK(BV_POWER_DC1LIMITS_POSLIMIT_BUCK__##e)
#define BFM_POWER_DC1LIMITS_POSLIMIT_BUCK_V(v)  BM_POWER_DC1LIMITS_POSLIMIT_BUCK
#define BP_POWER_DC1LIMITS_NEGLIMIT             0
#define BM_POWER_DC1LIMITS_NEGLIMIT             0x7f
#define BF_POWER_DC1LIMITS_NEGLIMIT(v)          (((v) & 0x7f) << 0)
#define BFM_POWER_DC1LIMITS_NEGLIMIT(v)         BM_POWER_DC1LIMITS_NEGLIMIT
#define BF_POWER_DC1LIMITS_NEGLIMIT_V(e)        BF_POWER_DC1LIMITS_NEGLIMIT(BV_POWER_DC1LIMITS_NEGLIMIT__##e)
#define BFM_POWER_DC1LIMITS_NEGLIMIT_V(v)       BM_POWER_DC1LIMITS_NEGLIMIT

#define HW_POWER_DC2LIMITS                      HW(POWER_DC2LIMITS)
#define HWA_POWER_DC2LIMITS                     (0x80044000 + 0x70)
#define HWT_POWER_DC2LIMITS                     HWIO_32_RW
#define HWN_POWER_DC2LIMITS                     POWER_DC2LIMITS
#define HWI_POWER_DC2LIMITS                     
#define BP_POWER_DC2LIMITS_EN_BOOST             24
#define BM_POWER_DC2LIMITS_EN_BOOST             0x1000000
#define BF_POWER_DC2LIMITS_EN_BOOST(v)          (((v) & 0x1) << 24)
#define BFM_POWER_DC2LIMITS_EN_BOOST(v)         BM_POWER_DC2LIMITS_EN_BOOST
#define BF_POWER_DC2LIMITS_EN_BOOST_V(e)        BF_POWER_DC2LIMITS_EN_BOOST(BV_POWER_DC2LIMITS_EN_BOOST__##e)
#define BFM_POWER_DC2LIMITS_EN_BOOST_V(v)       BM_POWER_DC2LIMITS_EN_BOOST
#define BP_POWER_DC2LIMITS_POSLIMIT_BOOST       16
#define BM_POWER_DC2LIMITS_POSLIMIT_BOOST       0x7f0000
#define BF_POWER_DC2LIMITS_POSLIMIT_BOOST(v)    (((v) & 0x7f) << 16)
#define BFM_POWER_DC2LIMITS_POSLIMIT_BOOST(v)   BM_POWER_DC2LIMITS_POSLIMIT_BOOST
#define BF_POWER_DC2LIMITS_POSLIMIT_BOOST_V(e)  BF_POWER_DC2LIMITS_POSLIMIT_BOOST(BV_POWER_DC2LIMITS_POSLIMIT_BOOST__##e)
#define BFM_POWER_DC2LIMITS_POSLIMIT_BOOST_V(v) BM_POWER_DC2LIMITS_POSLIMIT_BOOST
#define BP_POWER_DC2LIMITS_POSLIMIT_BUCK        8
#define BM_POWER_DC2LIMITS_POSLIMIT_BUCK        0x7f00
#define BF_POWER_DC2LIMITS_POSLIMIT_BUCK(v)     (((v) & 0x7f) << 8)
#define BFM_POWER_DC2LIMITS_POSLIMIT_BUCK(v)    BM_POWER_DC2LIMITS_POSLIMIT_BUCK
#define BF_POWER_DC2LIMITS_POSLIMIT_BUCK_V(e)   BF_POWER_DC2LIMITS_POSLIMIT_BUCK(BV_POWER_DC2LIMITS_POSLIMIT_BUCK__##e)
#define BFM_POWER_DC2LIMITS_POSLIMIT_BUCK_V(v)  BM_POWER_DC2LIMITS_POSLIMIT_BUCK
#define BP_POWER_DC2LIMITS_NEGLIMIT             0
#define BM_POWER_DC2LIMITS_NEGLIMIT             0x7f
#define BF_POWER_DC2LIMITS_NEGLIMIT(v)          (((v) & 0x7f) << 0)
#define BFM_POWER_DC2LIMITS_NEGLIMIT(v)         BM_POWER_DC2LIMITS_NEGLIMIT
#define BF_POWER_DC2LIMITS_NEGLIMIT_V(e)        BF_POWER_DC2LIMITS_NEGLIMIT(BV_POWER_DC2LIMITS_NEGLIMIT__##e)
#define BFM_POWER_DC2LIMITS_NEGLIMIT_V(v)       BM_POWER_DC2LIMITS_NEGLIMIT

#define HW_POWER_LOOPCTRL                       HW(POWER_LOOPCTRL)
#define HWA_POWER_LOOPCTRL                      (0x80044000 + 0x80)
#define HWT_POWER_LOOPCTRL                      HWIO_32_RW
#define HWN_POWER_LOOPCTRL                      POWER_LOOPCTRL
#define HWI_POWER_LOOPCTRL                      
#define HW_POWER_LOOPCTRL_SET                   HW(POWER_LOOPCTRL_SET)
#define HWA_POWER_LOOPCTRL_SET                  (HWA_POWER_LOOPCTRL + 0x4)
#define HWT_POWER_LOOPCTRL_SET                  HWIO_32_WO
#define HWN_POWER_LOOPCTRL_SET                  POWER_LOOPCTRL
#define HWI_POWER_LOOPCTRL_SET                  
#define HW_POWER_LOOPCTRL_CLR                   HW(POWER_LOOPCTRL_CLR)
#define HWA_POWER_LOOPCTRL_CLR                  (HWA_POWER_LOOPCTRL + 0x8)
#define HWT_POWER_LOOPCTRL_CLR                  HWIO_32_WO
#define HWN_POWER_LOOPCTRL_CLR                  POWER_LOOPCTRL
#define HWI_POWER_LOOPCTRL_CLR                  
#define HW_POWER_LOOPCTRL_TOG                   HW(POWER_LOOPCTRL_TOG)
#define HWA_POWER_LOOPCTRL_TOG                  (HWA_POWER_LOOPCTRL + 0xc)
#define HWT_POWER_LOOPCTRL_TOG                  HWIO_32_WO
#define HWN_POWER_LOOPCTRL_TOG                  POWER_LOOPCTRL
#define HWI_POWER_LOOPCTRL_TOG                  
#define BP_POWER_LOOPCTRL_TRAN_NOHYST           30
#define BM_POWER_LOOPCTRL_TRAN_NOHYST           0x40000000
#define BF_POWER_LOOPCTRL_TRAN_NOHYST(v)        (((v) & 0x1) << 30)
#define BFM_POWER_LOOPCTRL_TRAN_NOHYST(v)       BM_POWER_LOOPCTRL_TRAN_NOHYST
#define BF_POWER_LOOPCTRL_TRAN_NOHYST_V(e)      BF_POWER_LOOPCTRL_TRAN_NOHYST(BV_POWER_LOOPCTRL_TRAN_NOHYST__##e)
#define BFM_POWER_LOOPCTRL_TRAN_NOHYST_V(v)     BM_POWER_LOOPCTRL_TRAN_NOHYST
#define BP_POWER_LOOPCTRL_HYST_SIGN             29
#define BM_POWER_LOOPCTRL_HYST_SIGN             0x20000000
#define BF_POWER_LOOPCTRL_HYST_SIGN(v)          (((v) & 0x1) << 29)
#define BFM_POWER_LOOPCTRL_HYST_SIGN(v)         BM_POWER_LOOPCTRL_HYST_SIGN
#define BF_POWER_LOOPCTRL_HYST_SIGN_V(e)        BF_POWER_LOOPCTRL_HYST_SIGN(BV_POWER_LOOPCTRL_HYST_SIGN__##e)
#define BFM_POWER_LOOPCTRL_HYST_SIGN_V(v)       BM_POWER_LOOPCTRL_HYST_SIGN
#define BP_POWER_LOOPCTRL_EN_CMP_HYST           28
#define BM_POWER_LOOPCTRL_EN_CMP_HYST           0x10000000
#define BF_POWER_LOOPCTRL_EN_CMP_HYST(v)        (((v) & 0x1) << 28)
#define BFM_POWER_LOOPCTRL_EN_CMP_HYST(v)       BM_POWER_LOOPCTRL_EN_CMP_HYST
#define BF_POWER_LOOPCTRL_EN_CMP_HYST_V(e)      BF_POWER_LOOPCTRL_EN_CMP_HYST(BV_POWER_LOOPCTRL_EN_CMP_HYST__##e)
#define BFM_POWER_LOOPCTRL_EN_CMP_HYST_V(v)     BM_POWER_LOOPCTRL_EN_CMP_HYST
#define BP_POWER_LOOPCTRL_EN_DC2_RCSCALE        27
#define BM_POWER_LOOPCTRL_EN_DC2_RCSCALE        0x8000000
#define BF_POWER_LOOPCTRL_EN_DC2_RCSCALE(v)     (((v) & 0x1) << 27)
#define BFM_POWER_LOOPCTRL_EN_DC2_RCSCALE(v)    BM_POWER_LOOPCTRL_EN_DC2_RCSCALE
#define BF_POWER_LOOPCTRL_EN_DC2_RCSCALE_V(e)   BF_POWER_LOOPCTRL_EN_DC2_RCSCALE(BV_POWER_LOOPCTRL_EN_DC2_RCSCALE__##e)
#define BFM_POWER_LOOPCTRL_EN_DC2_RCSCALE_V(v)  BM_POWER_LOOPCTRL_EN_DC2_RCSCALE
#define BP_POWER_LOOPCTRL_EN_DC1_RCSCALE        26
#define BM_POWER_LOOPCTRL_EN_DC1_RCSCALE        0x4000000
#define BF_POWER_LOOPCTRL_EN_DC1_RCSCALE(v)     (((v) & 0x1) << 26)
#define BFM_POWER_LOOPCTRL_EN_DC1_RCSCALE(v)    BM_POWER_LOOPCTRL_EN_DC1_RCSCALE
#define BF_POWER_LOOPCTRL_EN_DC1_RCSCALE_V(e)   BF_POWER_LOOPCTRL_EN_DC1_RCSCALE(BV_POWER_LOOPCTRL_EN_DC1_RCSCALE__##e)
#define BFM_POWER_LOOPCTRL_EN_DC1_RCSCALE_V(v)  BM_POWER_LOOPCTRL_EN_DC1_RCSCALE
#define BP_POWER_LOOPCTRL_RC_SIGN               25
#define BM_POWER_LOOPCTRL_RC_SIGN               0x2000000
#define BF_POWER_LOOPCTRL_RC_SIGN(v)            (((v) & 0x1) << 25)
#define BFM_POWER_LOOPCTRL_RC_SIGN(v)           BM_POWER_LOOPCTRL_RC_SIGN
#define BF_POWER_LOOPCTRL_RC_SIGN_V(e)          BF_POWER_LOOPCTRL_RC_SIGN(BV_POWER_LOOPCTRL_RC_SIGN__##e)
#define BFM_POWER_LOOPCTRL_RC_SIGN_V(v)         BM_POWER_LOOPCTRL_RC_SIGN
#define BP_POWER_LOOPCTRL_EN_RCSCALE            24
#define BM_POWER_LOOPCTRL_EN_RCSCALE            0x1000000
#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)         (((v) & 0x1) << 24)
#define BFM_POWER_LOOPCTRL_EN_RCSCALE(v)        BM_POWER_LOOPCTRL_EN_RCSCALE
#define BF_POWER_LOOPCTRL_EN_RCSCALE_V(e)       BF_POWER_LOOPCTRL_EN_RCSCALE(BV_POWER_LOOPCTRL_EN_RCSCALE__##e)
#define BFM_POWER_LOOPCTRL_EN_RCSCALE_V(v)      BM_POWER_LOOPCTRL_EN_RCSCALE
#define BP_POWER_LOOPCTRL_DC2_FF                20
#define BM_POWER_LOOPCTRL_DC2_FF                0x700000
#define BF_POWER_LOOPCTRL_DC2_FF(v)             (((v) & 0x7) << 20)
#define BFM_POWER_LOOPCTRL_DC2_FF(v)            BM_POWER_LOOPCTRL_DC2_FF
#define BF_POWER_LOOPCTRL_DC2_FF_V(e)           BF_POWER_LOOPCTRL_DC2_FF(BV_POWER_LOOPCTRL_DC2_FF__##e)
#define BFM_POWER_LOOPCTRL_DC2_FF_V(v)          BM_POWER_LOOPCTRL_DC2_FF
#define BP_POWER_LOOPCTRL_DC2_R                 16
#define BM_POWER_LOOPCTRL_DC2_R                 0xf0000
#define BF_POWER_LOOPCTRL_DC2_R(v)              (((v) & 0xf) << 16)
#define BFM_POWER_LOOPCTRL_DC2_R(v)             BM_POWER_LOOPCTRL_DC2_R
#define BF_POWER_LOOPCTRL_DC2_R_V(e)            BF_POWER_LOOPCTRL_DC2_R(BV_POWER_LOOPCTRL_DC2_R__##e)
#define BFM_POWER_LOOPCTRL_DC2_R_V(v)           BM_POWER_LOOPCTRL_DC2_R
#define BP_POWER_LOOPCTRL_DC2_C                 12
#define BM_POWER_LOOPCTRL_DC2_C                 0x3000
#define BF_POWER_LOOPCTRL_DC2_C(v)              (((v) & 0x3) << 12)
#define BFM_POWER_LOOPCTRL_DC2_C(v)             BM_POWER_LOOPCTRL_DC2_C
#define BF_POWER_LOOPCTRL_DC2_C_V(e)            BF_POWER_LOOPCTRL_DC2_C(BV_POWER_LOOPCTRL_DC2_C__##e)
#define BFM_POWER_LOOPCTRL_DC2_C_V(v)           BM_POWER_LOOPCTRL_DC2_C
#define BP_POWER_LOOPCTRL_DC1_FF                8
#define BM_POWER_LOOPCTRL_DC1_FF                0x700
#define BF_POWER_LOOPCTRL_DC1_FF(v)             (((v) & 0x7) << 8)
#define BFM_POWER_LOOPCTRL_DC1_FF(v)            BM_POWER_LOOPCTRL_DC1_FF
#define BF_POWER_LOOPCTRL_DC1_FF_V(e)           BF_POWER_LOOPCTRL_DC1_FF(BV_POWER_LOOPCTRL_DC1_FF__##e)
#define BFM_POWER_LOOPCTRL_DC1_FF_V(v)          BM_POWER_LOOPCTRL_DC1_FF
#define BP_POWER_LOOPCTRL_DC1_R                 4
#define BM_POWER_LOOPCTRL_DC1_R                 0xf0
#define BF_POWER_LOOPCTRL_DC1_R(v)              (((v) & 0xf) << 4)
#define BFM_POWER_LOOPCTRL_DC1_R(v)             BM_POWER_LOOPCTRL_DC1_R
#define BF_POWER_LOOPCTRL_DC1_R_V(e)            BF_POWER_LOOPCTRL_DC1_R(BV_POWER_LOOPCTRL_DC1_R__##e)
#define BFM_POWER_LOOPCTRL_DC1_R_V(v)           BM_POWER_LOOPCTRL_DC1_R
#define BP_POWER_LOOPCTRL_DC1_C                 0
#define BM_POWER_LOOPCTRL_DC1_C                 0x3
#define BF_POWER_LOOPCTRL_DC1_C(v)              (((v) & 0x3) << 0)
#define BFM_POWER_LOOPCTRL_DC1_C(v)             BM_POWER_LOOPCTRL_DC1_C
#define BF_POWER_LOOPCTRL_DC1_C_V(e)            BF_POWER_LOOPCTRL_DC1_C(BV_POWER_LOOPCTRL_DC1_C__##e)
#define BFM_POWER_LOOPCTRL_DC1_C_V(v)           BM_POWER_LOOPCTRL_DC1_C

#define HW_POWER_STS                            HW(POWER_STS)
#define HWA_POWER_STS                           (0x80044000 + 0x90)
#define HWT_POWER_STS                           HWIO_32_RW
#define HWN_POWER_STS                           POWER_STS
#define HWI_POWER_STS                           
#define BP_POWER_STS_BATT_CHRG_PRESENT          31
#define BM_POWER_STS_BATT_CHRG_PRESENT          0x80000000
#define BF_POWER_STS_BATT_CHRG_PRESENT(v)       (((v) & 0x1) << 31)
#define BFM_POWER_STS_BATT_CHRG_PRESENT(v)      BM_POWER_STS_BATT_CHRG_PRESENT
#define BF_POWER_STS_BATT_CHRG_PRESENT_V(e)     BF_POWER_STS_BATT_CHRG_PRESENT(BV_POWER_STS_BATT_CHRG_PRESENT__##e)
#define BFM_POWER_STS_BATT_CHRG_PRESENT_V(v)    BM_POWER_STS_BATT_CHRG_PRESENT
#define BP_POWER_STS_MODE                       20
#define BM_POWER_STS_MODE                       0x300000
#define BF_POWER_STS_MODE(v)                    (((v) & 0x3) << 20)
#define BFM_POWER_STS_MODE(v)                   BM_POWER_STS_MODE
#define BF_POWER_STS_MODE_V(e)                  BF_POWER_STS_MODE(BV_POWER_STS_MODE__##e)
#define BFM_POWER_STS_MODE_V(v)                 BM_POWER_STS_MODE
#define BP_POWER_STS_BATT_BO                    16
#define BM_POWER_STS_BATT_BO                    0x10000
#define BF_POWER_STS_BATT_BO(v)                 (((v) & 0x1) << 16)
#define BFM_POWER_STS_BATT_BO(v)                BM_POWER_STS_BATT_BO
#define BF_POWER_STS_BATT_BO_V(e)               BF_POWER_STS_BATT_BO(BV_POWER_STS_BATT_BO__##e)
#define BFM_POWER_STS_BATT_BO_V(v)              BM_POWER_STS_BATT_BO
#define BP_POWER_STS_CHRGSTS                    14
#define BM_POWER_STS_CHRGSTS                    0x4000
#define BF_POWER_STS_CHRGSTS(v)                 (((v) & 0x1) << 14)
#define BFM_POWER_STS_CHRGSTS(v)                BM_POWER_STS_CHRGSTS
#define BF_POWER_STS_CHRGSTS_V(e)               BF_POWER_STS_CHRGSTS(BV_POWER_STS_CHRGSTS__##e)
#define BFM_POWER_STS_CHRGSTS_V(v)              BM_POWER_STS_CHRGSTS
#define BP_POWER_STS_DC2_OK                     13
#define BM_POWER_STS_DC2_OK                     0x2000
#define BF_POWER_STS_DC2_OK(v)                  (((v) & 0x1) << 13)
#define BFM_POWER_STS_DC2_OK(v)                 BM_POWER_STS_DC2_OK
#define BF_POWER_STS_DC2_OK_V(e)                BF_POWER_STS_DC2_OK(BV_POWER_STS_DC2_OK__##e)
#define BFM_POWER_STS_DC2_OK_V(v)               BM_POWER_STS_DC2_OK
#define BP_POWER_STS_DC1_OK                     12
#define BM_POWER_STS_DC1_OK                     0x1000
#define BF_POWER_STS_DC1_OK(v)                  (((v) & 0x1) << 12)
#define BFM_POWER_STS_DC1_OK(v)                 BM_POWER_STS_DC1_OK
#define BF_POWER_STS_DC1_OK_V(e)                BF_POWER_STS_DC1_OK(BV_POWER_STS_DC1_OK__##e)
#define BFM_POWER_STS_DC1_OK_V(v)               BM_POWER_STS_DC1_OK
#define BP_POWER_STS_VDDIO_BO                   9
#define BM_POWER_STS_VDDIO_BO                   0x200
#define BF_POWER_STS_VDDIO_BO(v)                (((v) & 0x1) << 9)
#define BFM_POWER_STS_VDDIO_BO(v)               BM_POWER_STS_VDDIO_BO
#define BF_POWER_STS_VDDIO_BO_V(e)              BF_POWER_STS_VDDIO_BO(BV_POWER_STS_VDDIO_BO__##e)
#define BFM_POWER_STS_VDDIO_BO_V(v)             BM_POWER_STS_VDDIO_BO
#define BP_POWER_STS_VDDD_BO                    8
#define BM_POWER_STS_VDDD_BO                    0x100
#define BF_POWER_STS_VDDD_BO(v)                 (((v) & 0x1) << 8)
#define BFM_POWER_STS_VDDD_BO(v)                BM_POWER_STS_VDDD_BO
#define BF_POWER_STS_VDDD_BO_V(e)               BF_POWER_STS_VDDD_BO(BV_POWER_STS_VDDD_BO__##e)
#define BFM_POWER_STS_VDDD_BO_V(v)              BM_POWER_STS_VDDD_BO
#define BP_POWER_STS_VDD5V_GT_VDDIO             4
#define BM_POWER_STS_VDD5V_GT_VDDIO             0x10
#define BF_POWER_STS_VDD5V_GT_VDDIO(v)          (((v) & 0x1) << 4)
#define BFM_POWER_STS_VDD5V_GT_VDDIO(v)         BM_POWER_STS_VDD5V_GT_VDDIO
#define BF_POWER_STS_VDD5V_GT_VDDIO_V(e)        BF_POWER_STS_VDD5V_GT_VDDIO(BV_POWER_STS_VDD5V_GT_VDDIO__##e)
#define BFM_POWER_STS_VDD5V_GT_VDDIO_V(v)       BM_POWER_STS_VDD5V_GT_VDDIO
#define BP_POWER_STS_AVALID                     3
#define BM_POWER_STS_AVALID                     0x8
#define BF_POWER_STS_AVALID(v)                  (((v) & 0x1) << 3)
#define BFM_POWER_STS_AVALID(v)                 BM_POWER_STS_AVALID
#define BF_POWER_STS_AVALID_V(e)                BF_POWER_STS_AVALID(BV_POWER_STS_AVALID__##e)
#define BFM_POWER_STS_AVALID_V(v)               BM_POWER_STS_AVALID
#define BP_POWER_STS_BVALID                     2
#define BM_POWER_STS_BVALID                     0x4
#define BF_POWER_STS_BVALID(v)                  (((v) & 0x1) << 2)
#define BFM_POWER_STS_BVALID(v)                 BM_POWER_STS_BVALID
#define BF_POWER_STS_BVALID_V(e)                BF_POWER_STS_BVALID(BV_POWER_STS_BVALID__##e)
#define BFM_POWER_STS_BVALID_V(v)               BM_POWER_STS_BVALID
#define BP_POWER_STS_VBUSVALID                  1
#define BM_POWER_STS_VBUSVALID                  0x2
#define BF_POWER_STS_VBUSVALID(v)               (((v) & 0x1) << 1)
#define BFM_POWER_STS_VBUSVALID(v)              BM_POWER_STS_VBUSVALID
#define BF_POWER_STS_VBUSVALID_V(e)             BF_POWER_STS_VBUSVALID(BV_POWER_STS_VBUSVALID__##e)
#define BFM_POWER_STS_VBUSVALID_V(v)            BM_POWER_STS_VBUSVALID
#define BP_POWER_STS_SESSEND                    0
#define BM_POWER_STS_SESSEND                    0x1
#define BF_POWER_STS_SESSEND(v)                 (((v) & 0x1) << 0)
#define BFM_POWER_STS_SESSEND(v)                BM_POWER_STS_SESSEND
#define BF_POWER_STS_SESSEND_V(e)               BF_POWER_STS_SESSEND(BV_POWER_STS_SESSEND__##e)
#define BFM_POWER_STS_SESSEND_V(v)              BM_POWER_STS_SESSEND

#define HW_POWER_SPEEDTEMP                  HW(POWER_SPEEDTEMP)
#define HWA_POWER_SPEEDTEMP                 (0x80044000 + 0xa0)
#define HWT_POWER_SPEEDTEMP                 HWIO_32_RW
#define HWN_POWER_SPEEDTEMP                 POWER_SPEEDTEMP
#define HWI_POWER_SPEEDTEMP                 
#define HW_POWER_SPEEDTEMP_SET              HW(POWER_SPEEDTEMP_SET)
#define HWA_POWER_SPEEDTEMP_SET             (HWA_POWER_SPEEDTEMP + 0x4)
#define HWT_POWER_SPEEDTEMP_SET             HWIO_32_WO
#define HWN_POWER_SPEEDTEMP_SET             POWER_SPEEDTEMP
#define HWI_POWER_SPEEDTEMP_SET             
#define HW_POWER_SPEEDTEMP_CLR              HW(POWER_SPEEDTEMP_CLR)
#define HWA_POWER_SPEEDTEMP_CLR             (HWA_POWER_SPEEDTEMP + 0x8)
#define HWT_POWER_SPEEDTEMP_CLR             HWIO_32_WO
#define HWN_POWER_SPEEDTEMP_CLR             POWER_SPEEDTEMP
#define HWI_POWER_SPEEDTEMP_CLR             
#define HW_POWER_SPEEDTEMP_TOG              HW(POWER_SPEEDTEMP_TOG)
#define HWA_POWER_SPEEDTEMP_TOG             (HWA_POWER_SPEEDTEMP + 0xc)
#define HWT_POWER_SPEEDTEMP_TOG             HWIO_32_WO
#define HWN_POWER_SPEEDTEMP_TOG             POWER_SPEEDTEMP
#define HWI_POWER_SPEEDTEMP_TOG             
#define BP_POWER_SPEEDTEMP_SPEED_STS1       24
#define BM_POWER_SPEEDTEMP_SPEED_STS1       0xff000000
#define BF_POWER_SPEEDTEMP_SPEED_STS1(v)    (((v) & 0xff) << 24)
#define BFM_POWER_SPEEDTEMP_SPEED_STS1(v)   BM_POWER_SPEEDTEMP_SPEED_STS1
#define BF_POWER_SPEEDTEMP_SPEED_STS1_V(e)  BF_POWER_SPEEDTEMP_SPEED_STS1(BV_POWER_SPEEDTEMP_SPEED_STS1__##e)
#define BFM_POWER_SPEEDTEMP_SPEED_STS1_V(v) BM_POWER_SPEEDTEMP_SPEED_STS1
#define BP_POWER_SPEEDTEMP_SPEED_STS2       16
#define BM_POWER_SPEEDTEMP_SPEED_STS2       0xff0000
#define BF_POWER_SPEEDTEMP_SPEED_STS2(v)    (((v) & 0xff) << 16)
#define BFM_POWER_SPEEDTEMP_SPEED_STS2(v)   BM_POWER_SPEEDTEMP_SPEED_STS2
#define BF_POWER_SPEEDTEMP_SPEED_STS2_V(e)  BF_POWER_SPEEDTEMP_SPEED_STS2(BV_POWER_SPEEDTEMP_SPEED_STS2__##e)
#define BFM_POWER_SPEEDTEMP_SPEED_STS2_V(v) BM_POWER_SPEEDTEMP_SPEED_STS2
#define BP_POWER_SPEEDTEMP_TEMP_STS         8
#define BM_POWER_SPEEDTEMP_TEMP_STS         0xf00
#define BF_POWER_SPEEDTEMP_TEMP_STS(v)      (((v) & 0xf) << 8)
#define BFM_POWER_SPEEDTEMP_TEMP_STS(v)     BM_POWER_SPEEDTEMP_TEMP_STS
#define BF_POWER_SPEEDTEMP_TEMP_STS_V(e)    BF_POWER_SPEEDTEMP_TEMP_STS(BV_POWER_SPEEDTEMP_TEMP_STS__##e)
#define BFM_POWER_SPEEDTEMP_TEMP_STS_V(v)   BM_POWER_SPEEDTEMP_TEMP_STS
#define BP_POWER_SPEEDTEMP_SPEED_CTRL       4
#define BM_POWER_SPEEDTEMP_SPEED_CTRL       0x30
#define BF_POWER_SPEEDTEMP_SPEED_CTRL(v)    (((v) & 0x3) << 4)
#define BFM_POWER_SPEEDTEMP_SPEED_CTRL(v)   BM_POWER_SPEEDTEMP_SPEED_CTRL
#define BF_POWER_SPEEDTEMP_SPEED_CTRL_V(e)  BF_POWER_SPEEDTEMP_SPEED_CTRL(BV_POWER_SPEEDTEMP_SPEED_CTRL__##e)
#define BFM_POWER_SPEEDTEMP_SPEED_CTRL_V(v) BM_POWER_SPEEDTEMP_SPEED_CTRL
#define BP_POWER_SPEEDTEMP_TEMP_CTRL        0
#define BM_POWER_SPEEDTEMP_TEMP_CTRL        0xf
#define BF_POWER_SPEEDTEMP_TEMP_CTRL(v)     (((v) & 0xf) << 0)
#define BFM_POWER_SPEEDTEMP_TEMP_CTRL(v)    BM_POWER_SPEEDTEMP_TEMP_CTRL
#define BF_POWER_SPEEDTEMP_TEMP_CTRL_V(e)   BF_POWER_SPEEDTEMP_TEMP_CTRL(BV_POWER_SPEEDTEMP_TEMP_CTRL__##e)
#define BFM_POWER_SPEEDTEMP_TEMP_CTRL_V(v)  BM_POWER_SPEEDTEMP_TEMP_CTRL

#define HW_POWER_BATTMONITOR                        HW(POWER_BATTMONITOR)
#define HWA_POWER_BATTMONITOR                       (0x80044000 + 0xb0)
#define HWT_POWER_BATTMONITOR                       HWIO_32_RW
#define HWN_POWER_BATTMONITOR                       POWER_BATTMONITOR
#define HWI_POWER_BATTMONITOR                       
#define BP_POWER_BATTMONITOR_BATT_VAL               16
#define BM_POWER_BATTMONITOR_BATT_VAL               0x3ff0000
#define BF_POWER_BATTMONITOR_BATT_VAL(v)            (((v) & 0x3ff) << 16)
#define BFM_POWER_BATTMONITOR_BATT_VAL(v)           BM_POWER_BATTMONITOR_BATT_VAL
#define BF_POWER_BATTMONITOR_BATT_VAL_V(e)          BF_POWER_BATTMONITOR_BATT_VAL(BV_POWER_BATTMONITOR_BATT_VAL__##e)
#define BFM_POWER_BATTMONITOR_BATT_VAL_V(v)         BM_POWER_BATTMONITOR_BATT_VAL
#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT        9
#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT        0x200
#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v)     (((v) & 0x1) << 9)
#define BFM_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v)    BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT
#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT_V(e)   BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(BV_POWER_BATTMONITOR_PWDN_BATTBRNOUT__##e)
#define BFM_POWER_BATTMONITOR_PWDN_BATTBRNOUT_V(v)  BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT
#define BP_POWER_BATTMONITOR_BRWNOUT_PWD            8
#define BM_POWER_BATTMONITOR_BRWNOUT_PWD            0x100
#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)         (((v) & 0x1) << 8)
#define BFM_POWER_BATTMONITOR_BRWNOUT_PWD(v)        BM_POWER_BATTMONITOR_BRWNOUT_PWD
#define BF_POWER_BATTMONITOR_BRWNOUT_PWD_V(e)       BF_POWER_BATTMONITOR_BRWNOUT_PWD(BV_POWER_BATTMONITOR_BRWNOUT_PWD__##e)
#define BFM_POWER_BATTMONITOR_BRWNOUT_PWD_V(v)      BM_POWER_BATTMONITOR_BRWNOUT_PWD
#define BP_POWER_BATTMONITOR_BRWNOUT_LVL            0
#define BM_POWER_BATTMONITOR_BRWNOUT_LVL            0xf
#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)         (((v) & 0xf) << 0)
#define BFM_POWER_BATTMONITOR_BRWNOUT_LVL(v)        BM_POWER_BATTMONITOR_BRWNOUT_LVL
#define BF_POWER_BATTMONITOR_BRWNOUT_LVL_V(e)       BF_POWER_BATTMONITOR_BRWNOUT_LVL(BV_POWER_BATTMONITOR_BRWNOUT_LVL__##e)
#define BFM_POWER_BATTMONITOR_BRWNOUT_LVL_V(v)      BM_POWER_BATTMONITOR_BRWNOUT_LVL

#define HW_POWER_RESET                  HW(POWER_RESET)
#define HWA_POWER_RESET                 (0x80044000 + 0xc0)
#define HWT_POWER_RESET                 HWIO_32_RW
#define HWN_POWER_RESET                 POWER_RESET
#define HWI_POWER_RESET                 
#define HW_POWER_RESET_SET              HW(POWER_RESET_SET)
#define HWA_POWER_RESET_SET             (HWA_POWER_RESET + 0x4)
#define HWT_POWER_RESET_SET             HWIO_32_WO
#define HWN_POWER_RESET_SET             POWER_RESET
#define HWI_POWER_RESET_SET             
#define HW_POWER_RESET_CLR              HW(POWER_RESET_CLR)
#define HWA_POWER_RESET_CLR             (HWA_POWER_RESET + 0x8)
#define HWT_POWER_RESET_CLR             HWIO_32_WO
#define HWN_POWER_RESET_CLR             POWER_RESET
#define HWI_POWER_RESET_CLR             
#define HW_POWER_RESET_TOG              HW(POWER_RESET_TOG)
#define HWA_POWER_RESET_TOG             (HWA_POWER_RESET + 0xc)
#define HWT_POWER_RESET_TOG             HWIO_32_WO
#define HWN_POWER_RESET_TOG             POWER_RESET
#define HWI_POWER_RESET_TOG             
#define BP_POWER_RESET_UNLOCK           16
#define BM_POWER_RESET_UNLOCK           0xffff0000
#define BV_POWER_RESET_UNLOCK__KEY      0x3e77
#define BF_POWER_RESET_UNLOCK(v)        (((v) & 0xffff) << 16)
#define BFM_POWER_RESET_UNLOCK(v)       BM_POWER_RESET_UNLOCK
#define BF_POWER_RESET_UNLOCK_V(e)      BF_POWER_RESET_UNLOCK(BV_POWER_RESET_UNLOCK__##e)
#define BFM_POWER_RESET_UNLOCK_V(v)     BM_POWER_RESET_UNLOCK
#define BP_POWER_RESET_PWD_OFF          4
#define BM_POWER_RESET_PWD_OFF          0x10
#define BF_POWER_RESET_PWD_OFF(v)       (((v) & 0x1) << 4)
#define BFM_POWER_RESET_PWD_OFF(v)      BM_POWER_RESET_PWD_OFF
#define BF_POWER_RESET_PWD_OFF_V(e)     BF_POWER_RESET_PWD_OFF(BV_POWER_RESET_PWD_OFF__##e)
#define BFM_POWER_RESET_PWD_OFF_V(v)    BM_POWER_RESET_PWD_OFF
#define BP_POWER_RESET_POR              3
#define BM_POWER_RESET_POR              0x8
#define BF_POWER_RESET_POR(v)           (((v) & 0x1) << 3)
#define BFM_POWER_RESET_POR(v)          BM_POWER_RESET_POR
#define BF_POWER_RESET_POR_V(e)         BF_POWER_RESET_POR(BV_POWER_RESET_POR__##e)
#define BFM_POWER_RESET_POR_V(v)        BM_POWER_RESET_POR
#define BP_POWER_RESET_PWD              2
#define BM_POWER_RESET_PWD              0x4
#define BF_POWER_RESET_PWD(v)           (((v) & 0x1) << 2)
#define BFM_POWER_RESET_PWD(v)          BM_POWER_RESET_PWD
#define BF_POWER_RESET_PWD_V(e)         BF_POWER_RESET_PWD(BV_POWER_RESET_PWD__##e)
#define BFM_POWER_RESET_PWD_V(v)        BM_POWER_RESET_PWD
#define BP_POWER_RESET_RST_DIG          1
#define BM_POWER_RESET_RST_DIG          0x2
#define BF_POWER_RESET_RST_DIG(v)       (((v) & 0x1) << 1)
#define BFM_POWER_RESET_RST_DIG(v)      BM_POWER_RESET_RST_DIG
#define BF_POWER_RESET_RST_DIG_V(e)     BF_POWER_RESET_RST_DIG(BV_POWER_RESET_RST_DIG__##e)
#define BFM_POWER_RESET_RST_DIG_V(v)    BM_POWER_RESET_RST_DIG
#define BP_POWER_RESET_RST_ALL          0
#define BM_POWER_RESET_RST_ALL          0x1
#define BF_POWER_RESET_RST_ALL(v)       (((v) & 0x1) << 0)
#define BFM_POWER_RESET_RST_ALL(v)      BM_POWER_RESET_RST_ALL
#define BF_POWER_RESET_RST_ALL_V(e)     BF_POWER_RESET_RST_ALL(BV_POWER_RESET_RST_ALL__##e)
#define BFM_POWER_RESET_RST_ALL_V(v)    BM_POWER_RESET_RST_ALL

#define HW_POWER_DEBUG                          HW(POWER_DEBUG)
#define HWA_POWER_DEBUG                         (0x80044000 + 0xd0)
#define HWT_POWER_DEBUG                         HWIO_32_RW
#define HWN_POWER_DEBUG                         POWER_DEBUG
#define HWI_POWER_DEBUG                         
#define HW_POWER_DEBUG_SET                      HW(POWER_DEBUG_SET)
#define HWA_POWER_DEBUG_SET                     (HWA_POWER_DEBUG + 0x4)
#define HWT_POWER_DEBUG_SET                     HWIO_32_WO
#define HWN_POWER_DEBUG_SET                     POWER_DEBUG
#define HWI_POWER_DEBUG_SET                     
#define HW_POWER_DEBUG_CLR                      HW(POWER_DEBUG_CLR)
#define HWA_POWER_DEBUG_CLR                     (HWA_POWER_DEBUG + 0x8)
#define HWT_POWER_DEBUG_CLR                     HWIO_32_WO
#define HWN_POWER_DEBUG_CLR                     POWER_DEBUG
#define HWI_POWER_DEBUG_CLR                     
#define HW_POWER_DEBUG_TOG                      HW(POWER_DEBUG_TOG)
#define HWA_POWER_DEBUG_TOG                     (HWA_POWER_DEBUG + 0xc)
#define HWT_POWER_DEBUG_TOG                     HWIO_32_WO
#define HWN_POWER_DEBUG_TOG                     POWER_DEBUG
#define HWI_POWER_DEBUG_TOG                     
#define BP_POWER_DEBUG_ENCTRLVBUS               4
#define BM_POWER_DEBUG_ENCTRLVBUS               0x10
#define BF_POWER_DEBUG_ENCTRLVBUS(v)            (((v) & 0x1) << 4)
#define BFM_POWER_DEBUG_ENCTRLVBUS(v)           BM_POWER_DEBUG_ENCTRLVBUS
#define BF_POWER_DEBUG_ENCTRLVBUS_V(e)          BF_POWER_DEBUG_ENCTRLVBUS(BV_POWER_DEBUG_ENCTRLVBUS__##e)
#define BFM_POWER_DEBUG_ENCTRLVBUS_V(v)         BM_POWER_DEBUG_ENCTRLVBUS
#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK         3
#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK         0x8
#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)      (((v) & 0x1) << 3)
#define BFM_POWER_DEBUG_VBUSVALIDPIOLOCK(v)     BM_POWER_DEBUG_VBUSVALIDPIOLOCK
#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK_V(e)    BF_POWER_DEBUG_VBUSVALIDPIOLOCK(BV_POWER_DEBUG_VBUSVALIDPIOLOCK__##e)
#define BFM_POWER_DEBUG_VBUSVALIDPIOLOCK_V(v)   BM_POWER_DEBUG_VBUSVALIDPIOLOCK
#define BP_POWER_DEBUG_AVALIDPIOLOCK            2
#define BM_POWER_DEBUG_AVALIDPIOLOCK            0x4
#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)         (((v) & 0x1) << 2)
#define BFM_POWER_DEBUG_AVALIDPIOLOCK(v)        BM_POWER_DEBUG_AVALIDPIOLOCK
#define BF_POWER_DEBUG_AVALIDPIOLOCK_V(e)       BF_POWER_DEBUG_AVALIDPIOLOCK(BV_POWER_DEBUG_AVALIDPIOLOCK__##e)
#define BFM_POWER_DEBUG_AVALIDPIOLOCK_V(v)      BM_POWER_DEBUG_AVALIDPIOLOCK
#define BP_POWER_DEBUG_BVALIDPIOLOCK            1
#define BM_POWER_DEBUG_BVALIDPIOLOCK            0x2
#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)         (((v) & 0x1) << 1)
#define BFM_POWER_DEBUG_BVALIDPIOLOCK(v)        BM_POWER_DEBUG_BVALIDPIOLOCK
#define BF_POWER_DEBUG_BVALIDPIOLOCK_V(e)       BF_POWER_DEBUG_BVALIDPIOLOCK(BV_POWER_DEBUG_BVALIDPIOLOCK__##e)
#define BFM_POWER_DEBUG_BVALIDPIOLOCK_V(v)      BM_POWER_DEBUG_BVALIDPIOLOCK
#define BP_POWER_DEBUG_SESSENDPIOLOCK           0
#define BM_POWER_DEBUG_SESSENDPIOLOCK           0x1
#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)        (((v) & 0x1) << 0)
#define BFM_POWER_DEBUG_SESSENDPIOLOCK(v)       BM_POWER_DEBUG_SESSENDPIOLOCK
#define BF_POWER_DEBUG_SESSENDPIOLOCK_V(e)      BF_POWER_DEBUG_SESSENDPIOLOCK(BV_POWER_DEBUG_SESSENDPIOLOCK__##e)
#define BFM_POWER_DEBUG_SESSENDPIOLOCK_V(v)     BM_POWER_DEBUG_SESSENDPIOLOCK

#endif /* __HEADERGEN_STMP3600_POWER_H__*/
